MT9173 Datasheet, PDF (1/22 Pages) Mitel Networks Corporation – Digital Subscriber Interface Circuit with RxSB

ISO²-CMOS ST-BUS™ FAMILY MT9173/74
®
Digital Subscriber Interface Circuit with RxSB
Digital Network Interface Circuit with RxSB
Features
• Receive sync output pulse
• Full duplex transmission over a single twisted
pair
• Selectable 80 or 160 kbit/s line rate
• Adaptive echo cancellation
• Up to 3km (9173) and 4 km (9174) loop reach
• ISDN compatible (2B+D) data format
• Transparent modem capability
• Frame synchronization and clock extraction
• MITEL ST-BUS compatible
• Low power (typically 50 mW), single 5V supply
Applications
• TDD Digital PCS (DECT, CT2, PHS) base
stations requiring cell synchronization
• Digital subscriber lines
• High speed data transmission over twisted
wires
• Digital PABX line cards and telephone sets
• 80 or 160 kbit/s single chip modem
ISSUE 2
March 1997
Ordering Information
MT9173AE
MT9173AN
MT9173AP
MT9174AE
MT9174AN
MT9174AP
24 Pin Plastic DIP (300mil)
24 Pin SSOP
28 Pin PLCC
24 Pin Plastic DIP (300 mil)
24 Pin SSOP
28 Pin PLCC
-40°C to +85°C
Description
The MT9173 (DSIC) and MT9174 (DNIC) are
functionally identical to the MT9171/72 except for the
addition of one feature. The MT9173/74 include a
digital output pin indicating the temporal position of
the received "SYNC" bit of the biphase transmission.
This feature is especially useful for systems such as
PCS wireless base station applications requiring
close synchronization between microcells.
The MT9173 and MT9174 are identical except for the
MT9173 having a shorter loop reach. The generic
"DNIC" will be used to reference both devices unless
otherwise noted. The MT9173/74 are fabricated in
Mitel’s ISO²-CMOS process.
DSTi/Di
CDSTi/
CDi
F0/CLD
C4/TCK
F0o/RCK
MS0
MS1
MS2
RegC
DSTo/Do
CDSTo/
CDo
RxSB
Transmit
Interface
Prescrambler
Scrambler
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
Control
Register
Transmit
Timing
Master Clock
Phase Locked
Transmit/
Clock
Receive
Timing &
Control _{Sync Detect}
DPLL
Status
Receive
Address
Echo Canceller
Error
Signal Echo Estimate
—
+
∑
Receive
Filter
V_Bias
MUX
-1
+2
Receive
Interface
De-
Prescrambler
Descrambler
Differentially
Encoded Biphase
Receiver
V_DD V_SS V_Bias V_Ref
Figure 1 - Functional Block Diagram
L_OUT
L_OUT
DIS
Precan
L_IN
OSC2
OSC1
9-137