PDSP16510AMA Datasheet, PDF (10/23 Pages) Mitel Networks Corporation – Stand Alone FFT Processor

PDSP16510A MA
input. When DEN and DOS are both active an internal read
operation occurs, and an address generator is incremented.
DAV goes in-active in response to the DOS edge needed to
read the last output, unless Bit 15 in the Control Register is set.
In this case DAV goes in-active when the next INEN edge is
received for reasons given later.
In host controlled systems the time to dump data could be
longer than the transform time. The dump time in such a
system will dictate the maximum sampling rate that can be
used without the loss of incoming data. In the 1024 point
mode, when the loss of data is not important, the PDSP16510
is designed to not accept new data until the previous results
have been dumped. Such a system needs no input buffer, and
INEN can be permanently tied low if the edge activated mode
is not in use. If the loss of data is to be avoided an input buffer
is needed and the host must have received all the results
before a new block of data has been loaded into the buffer.
For 256 point transforms, with host controlled dumping,
it is still possible to overlap load and dump operations. The
maximum dump times , however, must be less than the load
times to avoid data corruption. Previously converted outputs
will be actually corrupted , rather than inputs simply not being
used.
If the loss of incoming data is not important, the device
can be forced to do separate load, transform, and then dump
operations. The corruption of results will then never occur, no
matter what dump time is taken. This can be achieved by
ensuring that INEN is not active between loading a block of
data and completing the dump of the results from that data.
The same ends can be achieved if the INEN edge activated
mode ( Bit 12 reset ) is used, and the inverted DAV edge is
used to drive the INEN input. This then initializes a new load
operation only when the previous dump has been completed.
In such a system the INEN edge will be asynchronous to the
DIS strobe, and the set up time given in Table 1 may not be
obeyed. This will simply cause an extra input sample to be
possibly ignored, but will not cause data corruption.
Results are transferred from the device with the rising
edge of the DOS strobe when DEN is active. This is consistent
with using the device in a data flow architecture, as is com-
monly employed in data processing systems. In a typical
microprocessor based system, however, data is normally
expected to become valid before the end of the data strobe
produced by the processor. It is thus necessary for the user
to provide a ‘dummy’ data strobe in order to transfer data to
the outputs which can then be read by the host during the next
data strobe. In addition a further three ' dummy ' strobes are
needed each time DAV goes active in order to prime the output
circuitry. The actual output sequence is given in Table 3, and
illustrates that four DEN enabled DOS strobes are needed
before the first frequency bin appears on the output pins. This
is then read by the host with the fifth DOS strobe. DAV does
not go inactive until the DOS edge after the last bin appeared
on the output pins.
In addition to the above requirements it is necessary to
provide at least four DOS strobes after DEF has gone in-
active, but before DAV goes active. These initialize the
internal address counters and do not rely on DEN also being
active. They are needed every time DEF has been used to
change the operating mode.
Charactreristic
16510A
Symbol
Min Max
† DEN Set Up Time
† Host Strobe Width
† DEN Hold Time
† DAV in-active going Delay ( 30 pf load )
† Output Enable Time ( see Fig 13 )
† Output Data Delay Time ( 30 pf load )
† Output Disable Time ( see Fig 13 )
† Read Cycle Times
† Old Data Hold Time
T_PS
10
T_PW
10
T_PH
5
T_VI
10
T_LZ
10
T_DD
15
T
10
HZ
T
25
RC
T
2
OH
Table 3. Host Controlled Output Timing. ( Advanced Data )
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns