XP1005-BD Datasheet, PDF (5/7 Pages) Mimix Broadband – 35.0-43.0 GHz GaAs MMIC Power Amplifier

35.0-43.0 GHz GaAs MMIC
Power Amplifier
August 2007 - Rev 10-Aug-07
P1005-BD
App Note [1] Biasing - It is recommended to separately bias each amplifier stage Vd1 through Vd4 at Vd(1,2,3,4)=4.5V with Id1=35mA, Id2=65mA,
Id3=130mA and Id4=270mA. Separate biasing is recommended if the amplifier is to be used at high levels of saturation, where gate rectification will
alter the effective gate control voltage. For non-critical applications it is possible to parallel all stages and adjust the common gate voltage for a
total drain current Id(total)=500 mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature
vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may
be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The
gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage needed to do this is -0.7V.
Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative
gate bias is available before applying the positive drain supply.
App Note [2] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if gate or
drains are tied together) of DC bias pads. The Vg3a/b, Vd3a/b, Vg4a/b and Vd4a/b pads have been tied together on chip and can be biased from
either side. The unused Vg3a/b, Vd3a/b, Vg4a/b and Vd4a/b pads must be bypassed but can be left open.
For Individual Stage Bias (Recommended for saturated applications) -- Each DC pad (Vd1,2,3,4 and Vg1,2,3,4) needs to have DC bypass capacitance
(~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended. The Vg3a/b, Vd3a/b, Vg4a/b and
Vd4a/b pads have been tied together on chip and can be biased from either side. The unused Vg3a/b, Vd3a/b, Vg4a/b and Vd4a/b pads must be
bypassed but can be left open.
App Note [3] Output Power Adjust Using Gate Control - The XP1005 device has an interesting and very useful additional feature. The XP1005's
output power can be adjusted by lowering the individual or combined gate voltages towards pinch off without sacrificing much in the way of Input
3rd Order Intercept Point. Improvements to the IIP3 and Noise Figure data shown here while attenuating the gain are also possible with individual
gate control. Data here has been taken using combined gate control (all gates changed together) to lower the device's output power. The results are
shown in the table below. Additionally, the accompanying curve shows the level and linearity of the typical attenuation achievable as the gate is
adjusted at various levels until pinch-off.
Frequency: 40.0 GHz (worst case across 37.5-40.0 GHz) Pin: -19.0 dBm@scl Drain Voltage: 4.5 Volts
Id split: Vd1=35 mA, Vd2=65 mA, Vd3A=65.0 mA, Vd3B=65.0 mA, Vd4A=135 mA, Vd4B=135 mA
Gain (dB) IM3 (dBc) IIP3 (dBm) NF (dB)
Turning Off XP1005-BD on WP154_02 at Vds = 4.5 V, Pin = 5 dBm & Room Temperature
30
25
26.0
47.0
4.5
7.10
20
24.0
53.0
7.5
6.80
15
22.0
58.0
10.0
6.70
10
20.0
62.0
12.0
6.60
5
18.0
61.0
11.5
7.00
0
16.0
59.0
10.5
7.10
-5
14.0
58.0
10.0
7.50
-10
12.0
57.0
9.5
7.90
-15
10.0
57.0
9.5
8.80
-20
8.0
57.0
9.5
9.40
-25
R2C2 Ids = 500 mA
R2C2 Ids = 50%
R2C2 Ids = 25%
R2C2 Ids = 12.5%
R2C2 Ids = 6.25%
R2C2 Ids = 3.125%
R2C2 Vgs = -2.5 V
R3C3 Ids = 500 mA
R3C3 Ids = 50%
R3C3 Ids = 25%
R3C3 Ids = 12.5%
R3C3 Ids = 6.25%
R3C3 Ids = 3.125%
R3C3 Vgs = -2.5 V
MTTF Tables
-30
37
38
39
40
Frequency (GHz)
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
Channel
Temperature
Rth
MTTF Hours
FITs
55 deg Celsius
133.8 deg Celsius 35.0° C/W
3.35E+08
2.99E+00
75 deg Celsius
159.1 deg Celsius 37.4° C/W
2.45E+07
4.08E+01
95 deg Celsius
184.0 deg Celsius 39.5° C/W
2.50E+06
4.01E+02
Bias Conditions: Vd1=Vd2=Vd3a(or Vd3b)=Vd4a(or Vd4b)=4.5V
Id1=35 mA, Id2=65 mA, Id3a/b=130 mA, Id4a/b=270 mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: [phone] Fax: [phone] mimixbroadband.com
Page 5 of 7
Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
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