XP1003-BD Datasheet, PDF (4/6 Pages) Mimix Broadband – 27.0-35.0 GHz GaAs MMIC

27.0-35.0 GHz GaAs MMIC
Power Amplifier
April 2007 - Rev 02-Apr-07
P1003-BD
App Note [1] Biasing - It is recommended to separately bias the upper and lower amplifiers at Vd(1,2)=4.5V Id(1+2)=220mA, and
Vd(3,4)=4.5V Id(3+4)=220mA, although best performance will result in separately biasing Vd1 through Vd4, with Id1=Id3=110mA,
Id2=Id4=110mA. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary;
this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias
circuit may be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to
sense the current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate
voltage needed to do this is -0.7V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to
sequence the applied voltage to ensure negative gate bias is available before applying the positive drain supply.
App Note [2] On-board Detector - The output signal of the power amplifier is coupled via a 15dB directional coupler to a detector,
which comprises a diode connected to the signal path, and a second diode used to provide a temperature compensation signal. The
common bias terminal is Vin, and is nominally set to forward bias both diodes. The bias is normally provided in 1 of 2 ways. The Vin
port can be connected directly to a 1V bias, and given the internal series resistance, results in about 1mA of bias current. Alternatively,
Vin can be tied to the same voltage as Vd1-Vd4 through an external series resistor Rin in the range 3 - 6k .
App Note [3] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC
bypass capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or
combination (if gate or drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for Saturated Applications) -- Each DC pad (Vd1,2,3,4 and Vg1,2,3,4) needs to have DC
bypass capacitance (~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also
recommended.
MTTF Table
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
55 deg Celsius
75 deg Celsius
95 deg Celsius
Channel
Temperature
117 deg Celsius
141.3 deg Celsius
165.2 deg Celsius
Rth
31.3° C/W
33.5° C/W
35.5° C/W
MTTF Hours
FITs
2.35E+09
1.56E+08
1.46E+07
4.26E-01
6.40E+00
6.85E+01
Bias Conditions: Vd1=Vd2=Vd3=Vd4=4.5V, Id1=Id2=Id3=Id4=110 mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: [phone] Fax: [phone] mimixbroadband.com
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Characteristic Data and Specifications are subject to change without notice. ©2007 Mimix Broadband, Inc.
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