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XP1000 Datasheet, PDF (4/6 Pages) Mimix Broadband – 17.0-24.0 GHz GaAs MMIC Power Amplifier
17.0-24.0 GHz GaAs MMIC
Power Amplifier
May 2005 - Rev 05-May-05
Detector Curves
P1000
Typical Detector Characteristic
(LOG) Typical Detector Characteristic
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0.000
12 13 14 15 16 17 18 19 20 21 22 23
Total Output Power, dBm
2 tones each at 3dB below total output
1.000
0.100
0.010
0.001
12 13 14 15 16 17 18 19 20 21 22 23
Total Output Power, dBm
2 tones each at 3dB below total output
App Note [1] Biasing - As shown in the bonding diagram, it is recommended to separately bias the upper and lower amplifiers at
Vd(1+2)=5.5V Id(1+2)=215mA, and Vd(3+4)=5.5V Id(3+4)=215mA, although best performance will result in separately biasing Vd1 through
Vd4, with Id1=Id3=71mA, Id2=Id4=144mA. It is also recommended to use active biasing to keep the currents constant as the RF power and
temperature vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints,
the bias circuit may be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used
to sense the current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltage
needed to do this is -0.5V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the
applied voltage to ensure negative gate bias is available before applying the positive drain supply.
App Note [2] On-board Detector - The output signal of the power amplifier is coupled via a 15dB directional coupler to a detector, which
comprises a diode connected to the signal path, and a second diode used to provide a temperature compensation signal. The common bias
terminal is Vd5, and is nominally set to forward bias both diodes. The bias is normally provided in 1 of 2 ways. The Vd5 port can be connected
directly to a 1V bias, and given the internal series resistance, results in about 1mA of bias current. Alternatively, Vd5 can be tied to the same
voltage as Vd1-Vd4 through an external series resistor Rd in the range 3 - 6kΩ.
App Note [3] Bias Arrangement -
For Parallel Stage Bias (Recommended for general applications) -- The same as Individual Stage Bias but all the drain or gate pad DC bypass
capacitors (~100-200 pF) can be combined. Additional DC bypass capacitance (~0.01 uF) is also recommended to all DC or combination (if
gate or drains are tied together) of DC bias pads.
For Individual Stage Bias (Recommended for Saturated Applications) -- Each DC pad (Vd1,2,3,4 and Vg1,2,3,4)needs to have DC bypass
capacitance (~100-200 pF) as close to the device as possible. Additional DC bypass capacitance (~0.01 uF) is also recommended.
MTTF Table
These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry.
Backplate
Temperature
Channel
Temperature
Rth
MTTF Hours
FITs
55 deg Celsius
75 deg Celsius
95 deg Celsius
127 deg Celsius
147 deg Celsius
167 deg Celsius
-
30.1° C/W
-
9.11E+08
1.03E+08
1.42E+07
1.70E+00
9.71E+00
7.04E+01
Bias Conditions: Vd1=Vd2=Vd3=Vd4=5.5V, Id1=Id3=71 mA, Id2=Id4=144 mA
Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099
Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com
Page 4 of 6
Characteristic Data and Specifications are subject to change without notice. 2005 Mimix Broadband, Inc.
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