AX500-PQ208I Datasheet, PDF (98/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Detailed Specifications
Power-Down
RefCLK
155 MHz
Delay Line
FB
Delay Line
/i Delay
Match
/i
155 MHz
PLL
155 MHz
Yes
/7
DividerJ
6
Lock
930 MHz
132.8 MHz
/j
CLK1
/j Delay
Match
CLK2
5
6
3
FBMuxSel DelayLine
DividerI
+6
LowFreq
Osc
Figure 2-54 • Using the PLL 155 MHz In, 133 MHz Out
PowerDown
RefCLK
133 MHz
Delay Line
/i Delay
Match
PLL
FB
Delay Line
/j
FBMuxSel
5
DelayLine
6
DividerI
1
3
LowFreq
Osc
Figure 2-55 • Using the PLL Delaying the Reference Clock
DividerJ
6
Lock
CLK1
/j
/j Delay ^CLK2
Match
133 MHz
2-84
Revision 18