AX500-PQ208I Datasheet, PDF (57/262 Pages) Microsemi Corporation – Axcelerator Family FPGAs

Voltage-Referenced I/O Standards
Axcelerator Family FPGAs
GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It requires a differential
amplifier input buffer and an Open Drain output buffer. The VCCI pin should be connected to 2.5 V or
3.3 V. Note that 2.5 V GTL+ is not supported across the full military temperature range.
Table 2-37 • DC Input and Output Levels
Min., V
N/A
VIL
Max., V
VREF – 0.1
VIH
Min., V
VREF + 0.1
Max., V
N/A
VOL
Max., V
0.6
VOH
Min., V
NA
IOL
IOH
mA
mA
NA
NA
AC Loadings
Test Point
VTT
25
10 pF
Figure 2-19 • AC Test Loads
Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF – 0.2
VREF + 0.2
VREF
Note: * Measuring Point = VTRIP
VREF (typ) (V)
1.0
C_load (pF)
10
Timing Characteristics
Table 2-39 • 2.5 V GTL+ I/O Module
Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 2.3 V, T_J = 70°C
–2 Speed
–1 Speed
Std Speed
Parameter
Description
Min. Max. Min. Max. Min. Max.
2.5 V GTL+ I/O Module Timing
t_DP
Input Buffer
1.71
1.95
t_PY
Output Buffer
1.13
1.29
t_ICLKQ
Clock-to-Q for the I/O input register
0.67
0.77
t_OCLKQ
Clock-to-Q for the I/O output register and
0.67
0.77
the I/O enable register
2.29
1.52
0.90
0.90
t_SUD
t_SUE
t_HD
t_HE
t_CPWHL
t_CPWLH
t_WASYN
t_REASYN
t_HASYN
t_CLR
t_PRESET
Data Input Set-Up
Enable Input Set-Up
Data Input Hold
Enable Input Hold
Clock Pulse Width High to Low
Clock Pulse Width Low to High
Asynchronous Pulse Width
Asynchronous Recovery Time
Asynchronous Removal Time
Asynchronous Clear-to-Q
Asynchronous Preset-to-Q
0.23
0.27
0.31
0.26
0.30
0.35
0.00
0.00
0.00
0.00
0.00
0.00
0.39
0.39
0.39
0.39
0.39
0.39
0.37
0.37
0.37
0.13
0.15
0.17
0.00
0.00
0.00
0.23
0.27
0.31
0.23
0.27
0.31
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Revision 18
2- 43