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| A3P125-PQG208 Datasheet, PDF (97/220 Pages) Microsemi Corporation – Up to 144 kbits of True Dual-Port SRAM | |||
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ProASIC3 Flash Family FPGAs
CLK
Data
50%
50%
tSUD tHD
50%
0
50%
50%
50%
tCKMPWH tCKMPWL
50%
50% 50%
EN
PRE
CLR
Out
50%
tHE
tSUE
tWPRE tRECPRE
50%
50%
tWCLR
50%
tRECCLR
50%
tCLKQ
tPRE2Q
50%
50%
tCLR2Q
50%
tREMPRE
50%
tREMCLR
50%
Figure 2-26 ⢠Timing Model and Waveforms
Timing Characteristics
Table 2-106 ⢠Register Delays
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
â2 â1 Std. Units
tCLKQ
Clock-to-Q of the Core Register
0.55 0.63 0.74 ns
tSUD
Data Setup Time for the Core Register
0.43 0.49 0.57 ns
tHD
Data Hold Time for the Core Register
0.00 0.00 0.00 ns
tSUE
Enable Setup Time for the Core Register
0.45 0.52 0.61 ns
tHE
Enable Hold Time for the Core Register
0.00 0.00 0.00 ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.40 0.45 0.53 ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.40 0.45 0.53 ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00 0.00 0.00 ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.22 0.25 0.30 ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00 0.00 0.00 ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.22 0.25 0.30 ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.22 0.25 0.30 ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.22 0.25 0.30 ns
tCKMPWH Clock Minimum Pulse Width High for the Core Register
0.32 0.37 0.43 ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.36 0.41 0.48 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Revision 13
2- 83
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