A3P125-PQG208 Datasheet, PDF (53/220 Pages) Microsemi Corporation – Up to 144 kbits of True Dual-Port SRAM

ProASIC3 Flash Family FPGAs
Table 2-49 • Minimum and Maximum DC Input and Output Levels
Applicable to Standard I/O Banks
3.3 V
LVCMOS
Wide Range
Drive
Strength
Equiv.
Software
Default
VIL
Drive
Strength Min. Max.
Option¹ V
V
VIH
Min. Max.
V
V
VOL
Max.
V
VOH
Min.
V
IOL IOH IOSL
µA µA
Max.
mA⁴
IOSH IIL² IIH³
Max.
mA⁴ µA⁵ µA⁵
100 µA
2 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25
27
10 10
100 µA
4 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 25
27
10 10
100 µA
6 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51
54
10 10
100 µA
8 mA –0.3 0.8 2 3.6 0.2 VDD – 0.2 100 100 51
54
10 10
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
4. Currents are measured at 85°C junction temperature.
5. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
6. Software default selection highlighted in gray.
Revision 13
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