A3PE600-2PQ208 Datasheet, PDF (96/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

ProASIC3E DC and Switching Characteristics
Embedded FlashROM Characteristics
CLK
t_SU
t_HOLD
t_SU
t_HOLD
t_SU
t_HOLD
Address
Data
A₀
t_CKQ2
D₀
A₁
t_CKQ2
D₀
t_CKQ2
D₁
Figure 2-54 • Timing Diagram
Timing Characteristics
Table 2-102 • Embedded FlashROM Access Time
Parameter
Description
t_SU
t_HOLD
t_CK2Q
F_MAX
Address Setup Time
Address Hold Time
Clock to Out
Maximum Clock Frequency
–2
0.53
0.00
16.23
15
–1
0.61
0.00
18.48
15
Std.
0.71
0.00
21.73
15
Units
ns
ns
ns
MHz
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Characteristics" section on page 2-12 for more details.
Timing Characteristics
Table 2-103 • JTAG 1532
Commercial-Case Conditions: T_J = 70°C, VCC = 1.425 V
Parameter
Description
–2 –1 Std.
Units
t_DISU
Test Data Input Setup Time
0.50 0.57 0.67
ns
t_DIHD
Test Data Input Hold Time
1.00 1.13 1.33
ns
t_TMSSU
Test Mode Select Setup Time
0.50 0.57 0.67
ns
t_TMDHD
Test Mode Select Hold Time
1.00 1.13 1.33
ns
t_TCK2Q
Clock to Q (data out)
6.00 6.80 8.00
ns
t_RSTB2Q
Reset to Q (data out)
20.00 22.67 26.67
ns
F_TCKMAX
TCK Maximum Frequency
25.00 22.00 19.00
MHz
t_TRSTREM
ResetB Removal Time
0.00 0.00 0.00
ns
t_TRSTREC
ResetB Recovery Time
0.20 0.23 0.27
ns
t_TRSTMPW
ResetB Minimum Pulse
TBD TBD TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
2-82
Revision 13