A3PE600-2PQ208 Datasheet, PDF (159/162 Pages) Microsemi Corporation – ProASIC3E Flash Family FPGAs with Optional Soft ARM Support

Revision
Advance v0.5
(continued)
Advance v0.4
(October 2005)
Advance v0.3
ProASIC3E Flash Family FPGAs
Changes
Page
The "I/O User Input/Output" pin description was updated to include information on
what happens when the pin is unused.
2-50
The "JTAG Pins" section was updated to include information on what happens
when the pin is unused.
2-51
The "Programming" section was updated to include information concerning
serialization.
2-53
The "JTAG 1532" section was updated to include SAMPLE/PRELOAD
information.
2-54
The "DC and Switching Characteristics" chapter was updated with new Starting
information.
on page
3-1
Table 3-6 was updated.
3-5
In Table 3-10, PAC4 was updated.
3-8
Table 3-19 was updated.
3-20
The note in Table 3-24 was updated.
3-23
All Timing Characteristics tables were updated from LVTTL to Register Delays
3-26 to
3-64
The Timing Characteristics for RAM4K9, RAM512X18, and FIFO were updated.
3-74 to
3-79
F_TCKMAX was updated in Table 3-98.
The "Packaging Tables" table was updated.
3-80
ii
Figure 2-11 was updated.
The "Clock Resources (VersaNets)" section was updated.
The "VersaNet Global Networks and Spine Access" section was updated.
The "PLL Macro" section was updated.
Figure 2-27 was updated.
Figure 2-20 was updated.
Table 2-5 was updated.
Table 2-6 was updated.
The "FIFO Flag Usage Considerations" section was updated.
Table 2-33 was updated.
Figure 2-24 was updated.
The "Cold-Sparing Support" section is new.
Table 2-45 was updated.
Table 2-48 was updated.
Pin descriptions in the "JTAG Pins" section were updated.
The "Pin Descriptions" section was updated.
Table 3-7 was updated.
2-9
2-9
2-9
2-15
2-28
2-19
2-25
2-25
2-27
2-51
2-31
2-34
2-64
2-81
2-51
2-50
3-6
Revision 13
5-9