A40MX04-PLG44 Datasheet, PDF (67/142 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-34 • A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed Std Speed
–F Speed
Parameter / Description
CMOS Output Module Timing⁵
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_DLH
t_DHL
t_ENZH
t_ENZL
t_ENHZ
t_ENLZ
t_GLH
t_GHL
t_LCO
Data-to-Pad HIGH
Data-to-Pad LOW
Enable Pad Z to HIGH
Enable Pad Z to LOW
Enable Pad HIGH to Z
Enable Pad LOW to Z
G-to-Pad HIGH
G-to-Pad LOW
I/O Latch Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
3.2
3.6
4.0
4.7
6.6 ns
2.5
2.7
3.1
3.6
5.1 ns
2.7
3.0
3.4
4.0
5.6 ns
3.0
3.3
3.8
4.4
6.2 ns
5.4
6.0
6.8
8.0
11.2 ns
5.0
5.6
6.3
7.4
10.4 ns
5.1
5.6
6.4
7.5
10.5 ns
5.1
5.6
6.4
7.5
10.5 ns
5.7
6.3
7.1
8.4
11.9 ns
t_ACO
Array Clock-to-Out
(Pad-to-Pad), 64 Clock Loading
8.0
8.9
10.1
11.9
16.7 ns
d_TLH Capacitive Loading, LOW to HIGH
0.03
0.03
0.03
0.04
0.06 ns/pF
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, point and position whichever is
appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
Revision 11
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