A40MX04-PLG44 Datasheet, PDF (43/142 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
PCI System Timing Specification
Table 1-26 and Table 1-27 list the critical PCI timing parameters and the corresponding timing
parameters for the MX PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI
Target and Target+DMA Master interface. Contact your Microsemi sales representative for more
details.
Table 1-26 • Clock Specification for 33 MHz PCI
PCI
A42MX24
A42MX36
Symbol
t_CYC
t_HIGH
t_LOW
Parameter
CLK Cycle Time
CLK High Time
CLK Low Time
Min.
30
11
11
Max.
–
–
–
Min.
4.0
1.9
1.9
Max.
–
–
–
Min.
4.0
1.9
1.9
Max.
–
–
–
Units
ns
ns
ns
Table 1-27 • Timing Parameters for 33 MHz PCI
PCI
A42MX24 A42MX36
Symbol Parameter
Min. Max. Min. Max. Min. Max. Units
t_VAL
CLK to Signal Valid—Bused Signals
t_VAL(PTP) CLK to Signal Valid—Point-to-Point
2
11 2.0 9.0 2.0 9.0 ns
2 ² 12 2.0 9.0 2.0 9.0 ns
t_ON
Float to Active
t_OFF
Active to Float
2
– 2.0 4.0 2.0 4.0 ns
–
28 – 8.3¹ – 8.3¹ ns
t_SU
Input Set-Up Time to CLK—Bused Signals 7
– 1.5 – 1.5 – ns
t_SU(PTP) Input Set-Up Time to CLK—Point-to-Point 10, 12² – 1.5 – 1.5 –
ns
t_H
Input Hold to CLK
0
– 0 – 0 – ns
Notes:
1. T_OFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional
10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times
than do bussed signals. GNT# has a setup of 10; REW# has a setup of 12.
Revision 11
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