A2F500M3G-1FGG484 Datasheet, PDF (66/192 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC)

SmartFusion DC and Switching Characteristics
CLK
Data_F
1
Data_R 6
t_DDROSUD2 t_DDROHD2
2
3
4
t_DDROREMCLR ^tDDROHD1
7
8
9
CLR
t_DDROREMCLR
t_DDROCLR2Q
Out
t_DDROCLKQ
7
2
8
3
5
10
t_DDRORECCLR
9
4
11
10
Figure 2-22 • Output DDR Timing Diagram
Timing Characteristics
Table 2-77 • Output DDR Propagation Delays
Worst Commercial-Case Conditions: T_J = 85°C, Worst-Case VCC = 1.425 V
Parameter
Description
–1
Units
t_DDROCLKQ
Clock-to-Out of DDR for Output DDR
0.71
ns
t_DDROSUD1
Data_F Data Setup for Output DDR
0.38
ns
t_DDROSUD2
Data_R Data Setup for Output DDR
0.38
ns
t_DDROHD1
Data_F Data Hold for Output DDR
0.00
ns
t_DDROHD2
Data_R Data Hold for Output DDR
0.00
ns
t_DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.81
ns
t_DDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
t_DDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.23
ns
t_DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.22
ns
t_DDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR
0.36
ns
t_DDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR
0.32
ns
F_DDOMAX
Maximum Frequency for the Output DDR
350
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-9 for derating values.
2-54
Revision 10