A3PE3000L-1FG484I Datasheet, PDF (58/242 Pages) Microsemi Corporation – ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

ProASIC3L DC and Switching Characteristics
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low voltage transistor–transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. This standard uses an LVTTL input buffer and push-pull output buffer. Furthermore, all
LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range, as specified in the JESD8-A
specification.
Table 2-46 • Minimum and Maximum DC Input and Output Levels
Applicable to Pro I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL VOH IOL IOH
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V mA mA
4 mA
–0.3
0.8
2
3.6
0.4
2.4 4 4
6 mA
–0.3 0.8
2
3.6
0.4
2.4 8 8
8 mA
–0.3 0.8
2
3.6
0.4
2.4 12 12
12 mA
–0.3 0.8
2
3.6
0.4
2.4 16 16
16 mA
–0.3 0.8
2
3.6
0.4
2.4 24 24
24 mA
–0.3 0.8
2
3.6
0.4
2.4 24 24
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
IOSL
Max.
mA¹
25
51
103
132
268
27
IOSH
Max.
mA¹
27
54
109
127
181
25
IIL IIH
µA² µA²
10 10
10 10
10 10
10 10
10 10
10 10
Table 2-47 • Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL VOH IOL IOH
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
V mA mA
2 mA
–0.3
0.8
2
3.6
0.4
2.4 2 2
4 mA
–0.3
0.8
2
3.6
0.4
2.4 4 4
6 mA
–0.3
0.8
2
3.6
0.4
2.4 6 6
8 mA
–0.3
0.8
2
3.6
0.4
2.4 8 8
12 mA
–0.3
0.8
2
3.6
0.4
2.4 12 12
16 mA
–0.3
0.8
2
3.6
0.4
2.4 16 16
24 mA
–0.3
0.8
2
3.6
0.4
2.4 24 24
Notes:
1. Currents are measured at 100°C junction temperature and maximum voltage.
2. Currents are measured at 85°C junction temperature.
3. Software default selection highlighted in gray.
IOSL
Max.
mA¹
25
25
51
51
103
132
268
IOSH
Max.
mA¹
27
27
54
54
109
127
181
IIL IIH
µA² µA²
10 10
10 10
10 10
10 10
10 10
10 10
10 10
2-42
Revision 13