A3PE3000L-1FG484I Datasheet, PDF (34/242 Pages) Microsemi Corporation – ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

ProASIC3L DC and Switching Characteristics
User I/O Characteristics
Timing Model
LVPECL
(Applicable
to Advanced
I/O Banks only)
I/O Module
(Registered)
t_PY = 1.05 ns
DQ
Input LVTTL
Clock
tt_IISCULKDQ==00.2.264nnss
t_PY = 0.76 ns (Advanced I/O Banks)
I/O Module
(Non-Registered)
LVDS,
BLVDS,
M-LVDS
(Applicable for
Advanced I/O
Banks only)
t_PY = 1.20 ns
I/O Module
(Non-Registered)
Combinational Cell
Y
Combinational Cell
Y
LVPECL (Applicable to
Advanced I/O Banks Only)L
t_PD = 0.56 ns
Combinational Cell
t_PD = 0.49 ns
t_DP = 1.34 ns
I/O Module
(Non-Registered)
Y
LVTTLOHiugthpustledwrivreatsetrength ^{= 12 mA}
t_PD = 0.87 ns
t_DP = 2.64 ns (Advanced I/O Banks)
Combinational Cell
I/O Module
(Non-Registered)
Y
t_PD = 0.47 ns
Combinational Cell
LVTTLOHiugthpustledwrivreatsetrength ^{= 8 mA}
t_DP = 3.66 ns (Advanced I/O Banks)
I/O Module
(Non-Registered)
Y
t_PD = 0.47 ns
LVCMOS 1.5 V Output drive strength = 4 mA
High slew rate
t_DP = 3.97 ns (Advanced I/O Banks)
Register Cell _{Combinational Cell Register Cell}
DQ
Y
DQ
t_PD = 0.47 ns
t_CLKQ = 0.55 ns
t_SUD = 0.43 ns
Input LVTTL
Clock
t_CLKQ = 0.55 ns
t_SUD = 0.43 ns
Input LVTTL
Clock
I/O Module
(Registered)
DQ
LVTTL 3.3 V Output drive
strength = 12 mA High slew rate
t_DP = 2.64 ns
(Advanced I/O Banks)
t_OCLKQ = 0.59 ns
t_OSUD = 0.31 ns
t_PY = 0.76 ns
(Advanced I/O Banks)
t_PY = 0.76 ns
(Advanced I/O Banks)
Figure 2-3 • Timing Model
Operating Conditions: –1 Speed, Commercial Temperature Range (T_J = 70°C), Worst-Case
V_CC = 1.14 V
2-18
Revision 13