A42MX24-PQ208I Datasheet, PDF (56/142 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-32 • A42MX09 Timing Characteristics (Nominal 5.0 V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75 V, T_J = 70°C)
–3 Speed –2 Speed –1 Speed
Std Speed –F Speed
Parameter / Description
Logic Module Propagation Delays¹
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
t_PD1
Single Module
t_CO
Sequential Clock-to-Q
t_GO
Latch G-to-Q
t_RS
Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays2
1.2
1.3
1.3
1.4
1.2
1.4
1.2
1.6
1.5
1.8
2.5 ns
1.6
1.9
2.7 ns
1.6
1.8
2.6 ns
1.8
2.1
2.9 ns
t_RD1
FO = 1 Routing Delay
t_RD2
FO = 2 Routing Delay
t_RD3
FO = 3 Routing Delay
t_RD4
FO = 4 Routing Delay
t_RD8
FO = 8 Routing Delay
Logic Module Sequential Timing3, 4
0.7
0.8
0.9
1.0
1.2
1.3
1.4
1.5
2.3
2.6
0.9
1.0
1.4 ns
1.2
1.4
1.9 ns
1.5
1.7
2.4 ns
1.7
2.0
2.9 ns
2.9
3.4
4.8 ns
t_SUD
Flip-Flop (Latch)
Data Input Set-Up
0.3
0.4
0.4
0.5
0.7
ns
t_HD
Flip-Flop (Latch) Data Input Hold 0.0
0.0
0.0
0.0
0.0
ns
t_SUENA Flip-Flop (Latch) Enable Set-Up 0.4
0.5
0.5
0.6
0.8
ns
t_HENA Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t_WCLKA Flip-Flop (Latch) Clock Active
3.4
3.8
4.3
5.0
7.0
ns
Pulse Width
t_WASYN Flip-Flop (Latch) Asynchronous
4.5
4.9
5.6
6.6
9.2
ns
Pulse Width
t_A
Flip-Flop Clock Input Period
3.5
3.8
4.3
5.1
7.1
ns
t_INH
Input Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t_INSU Input Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
t_OUTH Output Buffer Latch Hold
0.0
0.0
0.0
0.0
0.0
ns
t_OUTSU Output Buffer Latch Set-Up
0.3
0.3
0.4
0.4
0.6
ns
f_MAX
Flip-Flop (Latch) Clock Frequency
268
244
224
195
117 MHz
Notes:
1. For dual-module macros, use t_PD1 + t_RD1 + t_PDn, t_CO + t_RD1 + t_PDn, or t_PD1 + t_RD1 + t_SUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules
can be obtained from the Timer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External
setup/hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external
PAD signal to the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
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Revision 11