A40MX04-PL44I Datasheet, PDF (53/143 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-31 • A40MX04 Timing Characteristics (Nominal 3.3 V Operation)
(Worst-Case Commercial Conditions, VCC = 3.0 V, T_J = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed
Min. Max. Min. Max. Min. Max.
Std Speed
Min. Max.
–F Speed
Min. Max.
Units
Logic Module Propagation Delays
t_PD1
Single Module
1.7
2.0
t_PD2
Dual-Module Macros
3.7
4.3
t_CO
Sequential Clock-to-Q
1.7
2.0
t_GO
Latch G-to-Q
1.7
2.0
t_RS
Flip-Flop (Latch) Reset-to-Q
1.7
2.0
Logic Module Predicted Routing Delays¹
2.3
2.7
3.7 ns
4.9
5.7
8.0 ns
2.3
2.7
3.7 ns
2.3
2.7
3.7 ns
2.3
2.7
3.7 ns
t_RD1
FO = 1 Routing Delay
t_RD2
FO = 2 Routing Delay
t_RD3
FO = 3 Routing Delay
t_RD4
FO = 4 Routing Delay
t_RD8
FO = 8 Routing Delay
Logic Module Sequential Timing²
1.9
2.2
2.7
3.1
3.4
3.9
4.1
4.8
7.1
8.1
2.5
3.0
4.2 ns
3.5
4.1
5.7 ns
4.4
5.2
7.3 ns
5.4
6.3
8.9 ns
9.2
10.9
15.2 ns
t_SUD
Flip-Flop (Latch)
Data Input Set-Up
4.3
5.0
5.6
6.6
9.2
ns
t_HD3
Flip-Flop (Latch) Data Input Hold 0.0
0.0
0.0
0.0
0.0
ns
t_SUENA Flip-Flop (Latch) Enable Set-Up 4.3
5.0
5.6
6.6
9.2
ns
t_HENA Flip-Flop (Latch) Enable Hold
0.0
0.0
0.0
0.0
0.0
ns
t_WCLKA Flip-Flop (Latch)
4.6
5.3
5.6
7.0
9.8
ns
Clock Active Pulse Width
t_WASYN Flip-Flop (Latch)
4.6
5.3
5.6
7.0
9.8
ns
Asynchronous Pulse Width
t_A
f_MAX
Flip-Flop Clock Input Period
6.8
7.8
8.9
Flip-Flop (Latch) Clock Frequency
109
101
(FO = 128)
10.4
14.6
ns
92
80
48 MHz
Input Module Propagation Delays
t_INYH
Pad-to-Y HIGH
1.0
1.1
1.3
1.5
2.1 ns
t_INYL
Pad-to-Y LOW
0.9
1.0
1.1
1.3
1.9 ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check
the hold time for this macro.
4. Delays based on 35 pF loading.
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Revision 12