A40MX04-PL44I Datasheet, PDF (141/143 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

Datasheet Information
Revision
v6.0
(continued)
v5.1
v5.0
Changes
Page
The "Development Tool Support" section was updated.
1-16
The Table 1-7 • Absolute Maximum Ratings for 42MX Devices* and the Table 1-6 • 1-17
Absolute Maximum Ratings for 40MX Devices* were updated.
The Table 1-9 • 5V TTL Electrical Specifications was updated.
1-18
The Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
1-20
In the "Mixed 5.0V/3.3V Electrical Specifications" section, Table 1-14 • Absolute
Maximum Ratings*, Table 1-15 • Recommended Operating Conditions, and
Table 1-16 • Mixed 5.0V/3.3V Electrical Specifications were updated.
1-21
Table 1-17 • DC Specification (5.0 V PCI Signaling)1 was updated.
1-23
Table 1-19 • DC Specification (3.3 V PCI Signaling)1 was updated.
1-24
The "Junction Temperature (TJ)" section, "Package Thermal Characteristics" section, 1-26
and the tables were updated.
Figure 1-16 • 40MX Timing Model* was updated.
1-27
Figure 1-18 • 42MX Timing Model (Logic Functions Using Quadrant Clocks) was 1-28
updated.
Figure 1-19 • 42MX Timing Model (SRAM Functions) was updated.
1-29
Figure 1-26 • Output Buffer Latches was updated.
1-32
Table 1-22 • 42MX Temperature and Voltage Derating Factors is new.
1-36
Table 1-23 • 40MX Temperature and Voltage Derating Factors is new.
1-36
The "Pin Descriptions" section was updated.
1-83
In the "PQ100" table, Pin 64 (42MX09 and 42MX16) has changed to LP.
2-10
In the "PQ160" table, Pin 61 (42MX09, 42MX16, and 42MX64) has changed to LP.
2-14
In the "PQ208" table, the following pins changed:
Pin 129 (42MX09, 42MX16, and 42MX64) has changed to LP.
Pin 198 (42MX09) has changed to I/O.
2-20
The n the "PQ240" table, Pin 91 (42MX36) has changed to LP.
2-27
In the "VQ100" table, Pin 62 (42MX09 and 42MX16) has changed to LP.
2-33
In the "TQ176" table, Pin 109 (42MX09 and 42MX16) has changed to LP.
2-35
In the "BG272" table, Pin K20 (42MX36) has changed to LP.
2-48
The "Low Power Mode" section was updated.
1-9
Footnote 8 in Table 1-9 • 5V TTL Electrical Specifications was updated.
1-18
Footnote 8 in Table 1-13 • 3.3V LVTTL Electrical Specifications was updated.
1-20
Because the changes in this data sheet are extensive and technical in nature, this ALL
should be viewed as a new document. Please read it as you would a datasheet that is
published for the first time.
Note that the “Package Characteristics and Mechanical Drawings” section has been
eliminated from the datasheet. The mechanical drawings are now contained in a
separate document, Package Mechanical Drawings, available on the Microsemi SoC
Products Group website.
3-2
Revision 12