A42MX24-2PQ160 Datasheet, PDF (52/143 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
Table 1-30 • A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (continued)
(Worst-Case Commercial Conditions, VCC = 4.75 V, T_J = 70°C)
Parameter / Description
–3 Speed –2 Speed –1 Speed Std Speed –F Speed
Units
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
CMOS Output Module Timing¹
t_DLH
Data-to-Pad HIGH
3.9
4.5
5.1
6.05
8.5 ns
t_DHL
Data-to-Pad LOW
3.4
3.9
4.4
5.2
7.3 ns
t_ENZH Enable Pad Z to HIGH
3.4
3.9
4.4
5.2
7.3 ns
t_ENZL Enable Pad Z to LOW
4.9
5.6
6.4
7.5
10.5 ns
t_ENHZ Enable Pad HIGH to Z
7.9
9.1
10.4
12.2
17.0 ns
t_ENLZ Enable Pad LOW to Z
5.9
6.8
7.7
9.0
12.6 ns
d_TLH Delta LOW to HIGH
0.03
0.04
0.04
0.05
0.07 ns/pF
d_THL Delta HIGH to LOW
0.02
0.02
0.03
0.03
0.04 ns/pF
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for
estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.
3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer utility from the Designer software to
check the hold time for this macro.
4. Delays based on 35 pF loading.
Revision 12
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