A42MX24-2PQ160 Datasheet, PDF (43/143 Pages) Microsemi Corporation – 40MX and 42MX FPGA Families

40MX and 42MX FPGA Families
PCI System Timing Specification
Table 1-26 and Table 1-27 list the critical PCI timing parameters and the corresponding timing parameters for the MX
PCI-compliant devices.
PCI Models
Microsemi provides synthesizable VHDL and Verilog-HDL models for a PCI Target interface, a PCI Target and
Target+DMA Master interface. Contact your Microsemi sales representative for more details.
Table 1-26 • Clock Specification for 33 MHz PCI
Symbol Parameter
PCI
Min.
Max.
t_CYC
t_HIGH
t_LOW
CLK Cycle Time
CLK High Time
CLK Low Time
30
–
11
–
11
–
A42MX24
Min.
Max.
4.0
–
1.9
–
1.9
–
A42MX36
Min.
Max.
4.0
–
1.9
–
1.9
–
Units
ns
ns
ns
Table 1-27 • Timing Parameters for 33 MHz PCI
Symbol Parameter
PCI
A42MX24 A42MX36
Units
Min. Max. Min. Max. Min. Max.
t_VAL
t_VAL(PTP)
CLK to Signal Valid—Bused Signals
CLK to Signal Valid—Point-to-Point
2
11 2.0 9.0 2.0 9.0 ns
2²
12 2.0 9.0 2.0 9.0 ns
t_ON
Float to Active
t_OFF
Active to Float
2
– 2.0 4.0 2.0 4.0 ns
–
28
– 8.3¹ – 8.3¹ ns
t_SU
t_SU(PTP)
Input Set-Up Time to CLK—Bused Signals
Input Set-Up Time to CLK—Point-to-Point
7
– 1.5 – 1.5 –
ns
10, 12² –
1.5
–
1.5
–
ns
t_H
Input Hold to CLK
0
–
0
–
0
–
ns
Notes:
1. T_OFF is system dependent. MX PCI devices have 7.4 ns turn-off time, reflection is typically an additional 10 ns.
2. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bussed
signals. GNT# has a setup of 10; REW# has a setup of 12.
1-39
Revision 12