A3P1000L-FGG256 Datasheet, PDF (50/242 Pages) Microsemi Corporation – ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

ProASIC3L DC and Switching Characteristics
Table 2-36 • I/O Output Buffer Maximum Resistances¹
Applicable to Pro I/Os
Standard
Drive Strength
R_{PU(LL-)D2OWN}
R_{P(UL)L3-UP}
3.3 V LVTTL / 3.3 V LVCMOS
4 mA
100
300
8 mA
50
150
12 mA
25
75
16 mA
17
50
24 mA
11
33
3.3 V LVCMOS Wide Range
100 µA
Same as regular 3.3 V LVCMOS Same as regular 3.3 V LVCMOS
2.5 V LVCMOS
4 mA
100
200
8 mA
50
100
12 mA
25
50
16 mA
20
40
24 mA
11
22
1.8 V LVCMOS
2 mA
200
225
4 mA
100
112
6 mA
50
56
8 mA
50
56
12 mA
20
22
16 mA
20
22
1.5 V LVCMOS
2 mA
200
224
4 mA
100
112
6 mA
67
75
8 mA
33
37
12 mA
33
37
1.2 V LVCMOS
2 mA
158
164
1.2 V LVCMOS Wide Range
100 µA
Same as regular 1.2 V LVCMOS Same as regular 1.2 V LVCMOS
3.3 V PCI/PCI-X
Per PCI/PCI-X
25
75
specification
3.3 V GTL
20 mA⁴
11
–
2.5 V GTL
20 mA⁴
14
–
3.3 V GTL+
35 mA
12
–
2.5 V GTL+
33 mA
15
–
HSTL (I)
8 mA
50
50
HSTL (II)
15 mA⁴
25
25
SSTL2 (I)
15 mA
27
31
SSTL2 (II)
18 mA
13
15
SSTL3 (I)
14 mA
44
69
SSTL3 (II)
21 mA
18
32
Notes:
1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend
on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer
resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx.
2. R_{(PULL-DOWN-MAX)} = (VOLspec) / IOLspec
3. R_{(PULL-UP-MAX)} = (VCCImax – VOHspec) / IOHspec
4. Output drive strength is below JEDEC specification.
2-34
Revision 13