A3P1000L-FGG256 Datasheet, PDF (145/242 Pages) Microsemi Corporation – ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

ProASIC3L Low Power Flash FPGAs
Table 2-206 • A3P600L Global Resource – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T_J = 70°C, VCC = 1.425 V
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
t_RCKH
t_RCKMPWH
t_RCKMPWL
t_RCKSW
Notes:
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
0.90 1.14 1.06 1.34 ns
0.89 1.17 1.04 1.38 ns
0.75
0.88
ns
0.85
1.00
ns
0.28
0.33 ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Table 2-207 • A3P600L Global Resource – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: T_J = 70°C, VCC = 1.14 V
–1
Std.
Parameter
Description
Min.¹ Max.² Min.¹ Max.² Units
t_RCKL
t_RCKH
t_RCKMPWH
t_RCKMPWL
t_RCKSW
Notes:
Input Low Delay for Global Clock
Input High Delay for Global Clock
Minimum Pulse Width High for Global Clock
Minimum Pulse Width Low for Global Clock
Maximum Skew for Global Clock
1.48 1.76 1.74 2.07 ns
1.47 1.80 1.72 2.11 ns
1.05
1.24
ns
1.23
1.44
ns
0.33
0.39 ns
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential
element, located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,
located in a fully loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating
values.
Revision 13
2- 129