A3PN030-ZQNG48 Datasheet, PDF (35/114 Pages) Microsemi Corporation – ProASIC3 nano Flash FPGAs

ProASIC3 nano Flash FPGAs
Table 2-25 • Schmitt Trigger Input Hysteresis
Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers
Input Buffer Configuration
Hysteresis Value (typ.)
3.3 V LVTTL / LVCMOS (Schmitt trigger mode)
240 mV
2.5 V LVCMOS (Schmitt trigger mode)
140 mV
1.8 V LVCMOS (Schmitt trigger mode)
80 mV
1.5 V LVCMOS (Schmitt trigger mode)
60 mV
Table 2-26 • I/O Input Rise Time, Fall Time, and Related I/O Reliability
Input Buffer
Input Rise/Fall Time (min.) Input Rise/Fall Time (max.)
Reliability
LVTTL/LVCMOS
(Schmitt trigger
disabled)
No requirement
10 ns *
20 years (100°C)
LVTTL/LVCMOS
(Schmitt trigger
enabled)
No requirement
No requirement, but input
noise voltage cannot exceed
Schmitt hysteresis
20 years (100°C)
Note:
The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the
noise is low, then the rise time and fall time of input buffers can be increased beyond the
maximum value. The longer the rise/fall times, the more susceptible the input signal is to the
board noise. Microsemi recommends signal integrity evaluation/characterization of the system to
ensure that there is no excessive noise coupling into input signals.
Revision 11
2- 21