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A3P250-VQG100I Datasheet, PDF (33/220 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support | |||
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ProASIC3 Flash Family FPGAs
Table 2-19 ⢠Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and
Industrial ConditionsâSoftware Default Settings
Applicable to Standard Plus I/O Banks
Equiv.
Software
Default
Drive
Drive Strength Slew Min.
I/O Standard Strength Option2 Rate V
VIL
Max.
V
VIH
VOL
Min.
V
Max.
V
Max.
V
VOH
IOH
IOL1 1
Min.
V
mA mA
3.3 V LVTTL / 12 mA 12 mA High â0.3
0.8
3.3 V
LVCMOS
2
3.6
0.4
2.4
12 12
3.3 V
100 µA 12 mA High â0.3
0.8
LVCMOS
Wide Range3
2
3.6
0.2
VCCI â 0.2 0.1 0.1
2.5 V
LVCMOS
12 mA 12 mA High â0.3
0.7
1.7
2.7
0.7
1.7
12 12
1.8 V
LVCMOS
8 mA 8 mA High â0.3 0.35 * VCCI 0.65 * VCCI 1.9
0.45 VCCI â 0.45 8 8
1.5 V
LVCMOS
4 mA 4 mA High â0.3 0.35 * VCCI 0.65 * VCCI 1.6 0.25 * VCCI 0.75 * VCCI 4 4
3.3 V PCI
Per PCI specifications
3.3 V PCI-X
Per PCI-X specifications
Notes:
1. Currents are measured at 85°C junction temperature.
2. Please note that 3.3 V LVCMOS wide range is applicable to 100 µA drive strength only. The configuration will NOT
operate at the equivalent software default drive strength. These values are for Normal Ranges ONLY.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
Revision 13
2- 19
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