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A3P250-VQG100I Datasheet, PDF (108/220 Pages) Microsemi Corporation – ProASIC3 Flash Family FPGAs with Optional Soft ARM Support
ProASIC3 DC and Switching Characteristics
CLK
tCKH
tCYC
tCKL
RESET
DOUT|RD
Dm
tRSTBQ
Dn
Figure 2-34 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18.
Timing Characteristics
Table 2-116 • RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2 –1 Std. Units
tAS
tAH
tENS
tENH
tBKS
tBKH
tDS
tDH
tCKQ1
Address setup time
Address hold time
REN, WEN setup time
REN, WEN hold time
BLK setup time
BLK hold time
Input data (DIN) setup time
Input data (DIN) hold time
Clock High to new data valid on DOUT (output retained, WMODE = 0)
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
0.25 0.28 0.33 ns
0.00 0.00 0.00 ns
0.14 0.16 0.19 ns
0.10 0.11 0.13 ns
0.23 0.27 0.31 ns
0.02 0.02 0.02 ns
0.18 0.21 0.25 ns
0.00 0.00 0.00 ns
2.36 2.68 3.15 ns
1.79 2.03 2.39 ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
0.89 1.02 1.20 ns
tC2CWWL1 Address collision clk-to-clk delay for reliable write after write on same 0.33 0.28 0.25 ns
address—Applicable to Closing Edge
tC2CWWH1 Address collision clk-to-clk delay for reliable write after write on same 0.30 0.26 0.23 ns
address—Applicable to Rising Edge
tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same 0.45 0.38 0.34 ns
address—Applicable to Opening Edge
tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same 0.49 0.42 0.37 ns
address— Applicable to Opening Edge
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
RESET Low to Data Out Low on DOUT (pipelined)
0.92 1.05 1.23 ns
0.92 1.05 1.23 ns
tREMRSTB RESET removal
0.29 0.33 0.38 ns
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
2-94
Revision 13