A3P015-QNG68 Datasheet, PDF (114/220 Pages) Microsemi Corporation – 15 k to 1 M System Gates, Up to 144 kbits of True Dual-Port SRAM

ProASIC3 DC and Switching Characteristics
WCLK
FULL
AFULL
t_CYC
t_CKAF
t_WCKFF
(Address CWouAn/tRerA) ^{NO MATCH}
NO MATCH
Figure 2-40 • FIFO FULL Flag and AFULL Flag Assertion
Dist = AFF_TH
MATCH (FULL)
WCLK
(Address CWouAn/tRerA)
MATCH
(EMPTY)
NO MATCH
RCLK
1st Rising
Edge
After 1st
Write
NO MATCH
2nd Rising
Edge
After 1st
Write
t_RCKEF
EMPTY
NO MATCH
AEMPTY
Figure 2-41 • FIFO EMPTY Flag and AEMPTY Flag Deassertion
NO MATCH
Dist = AEF_TH + 1
t_CKAF
RCLK
WA/RA
(Address Counter)
WCLK
MATCH (FULL)
NO MATCH
1st Rising
Edge
After 1st
Read
FULL
NO MATCH
1st Rising
Edge
After 2nd
Read
t_WCKF
NO MATCH
AFULL
Figure 2-42 • FIFO FULL Flag and AFULL Flag Deassertion
NO MATCH
Dist = AFF_TH – 1
t_CKAF
2-100
Revision 13