A2F500M3G-FGG484 Datasheet, PDF (1/192 Pages) Microsemi Corporation – SmartFusion Customizable System-on-Chip (cSoC)

Revision 10
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS)
• Hard 100 MHz 32-Bit ARM^® Cortex™-M3
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
• Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
• Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,¹ Allowing Multi-Master Schemes
• 10/100 Ethernet MAC with RMII Interface²
• Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
• Two I²C Peripherals
• Two 16550 Compatible UARTs
• Two SPI Peripherals
• Two 32-Bit Timers
• 32-Bit Watchdog Timer
• 8-Channel DMA Controller to Offload the Cortex-M3
from Data Transactions
• Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
High-Performance FPGA
• Based on proven ProASIC^®3 FPGA Fabric
• Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
• Nonvolatile, Instant On, Retains Program When
Powered Off
• 350 MHz System Performance
• Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
– Programmable Embedded FIFO Control Logic
• Secure ISP with 128-Bit AES via JTAG
• FlashLock^® to Secure FPGA Contents
• Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
Programmable Analog
Analog Front-End (AFE)
• Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
• Internal 2.56 V Reference or Optional External
Reference
• One First-Order  DAC (sigma-delta) per ADC
– 8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate
• Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
– High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
• Up to Ten High-Speed Voltage Comparators
(t_pd = 15 ns)
Analog Compute Engine (ACE)
• Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
• Sample Sequence Engine for ADC and DAC Parameter
Set-Up
• Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
• Easily Configured via GUI in Libero^® System-on-Chip
(SoC) Software
I/Os and Operating Voltage
• FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
– Up to 350 MHz
• MSS I/Os
– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
– Up to 180 MHz
• Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
• External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
1 Theoretical maximum
2 A2F200 and larger devices
January 2013
I
© 2013 Microsemi Corporation