MSP3411G Datasheet, PDF (85/102 Pages) Micronas – Multistandard Sound Processor Family with Virtual Dolby Surround

PRELIMINARY DATA SHEET
MSP 34x1G
6.2. DSP Write and Read Registers for Manual/Compatibility Mode
Table 6–3: DSP-Write Registers; Subaddress: 12_hex, all registers are readable as well
Write Register
Volume SCART1 channel: Ctrl. mode
FM Fixed Deemphasis
FM Adaptive Deemphasis
Identification Mode
FM DC Notch
Volume SCART2 channel: Ctrl. mode
Address Bits
(hex)
00 07
[7..0]
00 0F
[15..8]
[7..0]
00 15
[7..0]
00 17
[7..0]
00 40
[7..0]
Operational Modes and Adjustable Range
[Linear mode / logarithmic mode]
[50 µs, 75 µs, OFF]
[OFF, WP1]
[B/G, M]
[ON, OFF]
[Linear mode / logarithmic mode]
Reset
Mode
00_hex
50 µs
OFF
B/G
ON
00_hex
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Table 6–4: DSP Read Registers; Subaddress: 13_hex, all registers are not writable
Additional Read Registers
Stereo detection register for
A2 Stereo Systems
DC level readout FM1/Ch2-L
DC level readout FM2/Ch1-R
Address Bits
(hex)
00 18
[15..8]
00 1B
00 1C
[15..0]
[15..0]
Output Range
[80_hex ... 7F_hex]
[8000_hex ... 7FFF_hex]
[8000_hex ... 7FFF_hex]
8 bit two’s complement
16 bit two’s complement
16 bit two’s complement
Page
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MICRONAS INTERMETALL
85