MSP3438G Datasheet, PDF (19/84 Pages) Micronas – Multistandard Sound Processor Family

PRELIMINARY DATA SHEET
MSP 3438G
Table 3–4: List of MSP 34x8G Write Registers, continued
Write Register
Volume SCART2 output channel
SCART2 source select
SCART2 channel matrix
Address Bits
(hex)
Description and Adjustable Range
00 40
00 41
[15..8]
[15..8]
[+12 dB ... −114 dB, MUTE]
[FM/AM, NICAM, SCART, I²S1..3, Mix output]
[7..0] [SOUNDA, SOUNDB, STEREO, MONO]
Reset
00_hex
FM
SOUNDA
See
Page
29
27
27
Table 3–5: List of MSP 34x8G Read Registers
Read Register
Address Bits
(hex)
I²C Subaddress = 11_hex ; Registers are not writable
STANDARD RESULT
00 7E
[15..0]
Description and Adjustable Range
Result of Automatic Standard Detection (see Table 3–7)
STATUS
02 00
[15..0]
I²C Subaddress = 13_hex ; Registers are not writable
Quasi peak readout left
00 19
[15..0]
Quasi peak readout right
00 1A
[15..0]
MSP hardware version code
00 1E
[15..8]
MSP major revision code
[7..0]
MSP product code
00 1F
[15..8]
MSP ROM version code
[7..0]
Monitoring of settings e.g. Stereo, Mono, Mute, D_CTR_I/O etc. .
[00_hex ... 7FFF_hex]16 bit two’s complement
[00_hex ... 7FFF_hex]16 bit two’s complement
[00_hex ... FF_hex]
[00_hex ... FF_hex]
[00_hex ... FF_hex]
[00_hex ... FF_hex]
See
Page
24
24
31
31
32
32
32
32
MICRONAS INTERMETALL
19