MSP3438G Datasheet, PDF (16/84 Pages) Micronas – Multistandard Sound Processor Family

MSP 3438G
Table 3–3: Control Register (Subaddress: 00_hex)
Name
Subaddress
15 (MSB)
14
CONTROL
00 hex
1 : RESET
0
0 : normal
PRELIMINARY DATA SHEET
13..1
0
0 (LSB)
0
3.1.2. Protocol Description
Write to DSP or Demodulator
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P
device
high
low
high
low
address
Read from DSP or Demodulator
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S read Wait ACK data-byte- ACK data-byte NAK P
device
high
low
device
high
low
address
address
Write to Control or Test Registers
S write Wait ACK sub-addr ACK data-byte ACK data-byte ACK P
device
high
low
address
Note: S =
P=
ACK =
NAK =
Wait =
I²C-Bus Start Condition from master
I²C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray)
or master (= controller dark gray)
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from MSP indicating internal error state
I²C-Clock line is held low, while the MSP is processing the I²C command. This waiting time is
max. 1 ms.
I2C_DA
1
0
S
P
I2C_CL
Fig. 3–1: I²C bus protocol (MSB first; data must be stable while clock is high)
16
MICRONAS INTERMETALL