TS5A21366_1 Datasheet, PDF (95/131 Pages) Texas Instruments – 0.75-Ω DUAL SPST ANALOG SWITCH WITH 1.8-V COMPATIBLE INPUT LOGIC

1Gb: x4, x8, x16 DDR2 SDRAM
READ
not be issued until ^tRP is met. However, part of the row precharge time is hidden during
the access of the last data elements.
Examples of READ-to-PRECHARGE for BL = 4 are shown in Figure 50 and in Figure 51
for BL = 8. The delay from READ-to-PRECHARGE period to the same bank is AL + BL/
2 - 2CK + MAX (^tRTP/^tCK or 2 × CK) where MAX means the larger of the two.
Figure 50: READ-to-PRECHARGE – BL = 4
CK#
CK
Command
4-bit
prefetch
T0
T1
T2
T3
READ
NOP
NOP
PRE
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address Bank a
Bank a
A10
Valid
AL = 1
CL = 3
DQS, DQS#
DQ
≥^tRTP (MIN)
≥^tRAS (MIN)
≥^tRC (MIN)
T4
T5
T6
NOP
NOP
ACT
Bank a
Valid
DO DO DO DO
≥^tRP (MIN)
Transitioning Data
Notes:
1. RL = 4 (AL = 1, CL = 3); BL = 4.
2. ^tRTP ≥ 2 clocks.
3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
T7
NOP
Don’t Care
Figure 51: READ-to-PRECHARGE – BL = 8
First 4-bit
Second 4-bit
prefetch
prefetch
CK# ^T0
T1
T2
T3
T4
T5
T6
CK
Command READ
NOP
NOP
NOP
NOP
PRE
NOP
AL + BL/2 - 2CK + MAX (tRTP/tCK or 2CK)
Address Bank a
Bank a
T7
T8
NOP
ACT
Bank a
A10
DQS, DQS#
DQ
AL = 1
CL = 3
Valid
Valid
DO DO
≥tRTP (MIN)
≥tRAS (MIN)
≥tRC (MIN)
DO DO DO DO DO DO
≥tRP (MIN)
Notes:
1. RL = 4 (AL = 1, CL = 3); BL = 8.
2. ^tRTP ≥ 2 clocks.
3. Shown with nominal ^tAC, ^tDQSCK, and ^tDQSQ.
Transitioning Data
Don’t Care
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
95
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