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| TS5A21366_1 Datasheet, PDF (64/131 Pages) Texas Instruments – 0.75-Ω DUAL SPST ANALOG SWITCH WITH 1.8-V COMPATIBLE INPUT LOGIC | |||
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1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 27: Nominal Slew Rate for tDS
DQS1
DQS#1
VDDQ
tDS
tDH
VIH(AC)min
VREF to AC
region
tDS
tDH
VIH(DC)min
VREF(DC)
Nominal
slew rate
Nominal
slew rate
VIL(DC)max
VIL(AC)max
VREF to AC
region
VSS
ÎTF
Setup slew rate
falling signal
=
VREF(DC) - VIL(AC)max
ÎTF
ÎTR
Setup slew rate
rising signal
=
VIH(AC)min - VREF(DC)
ÎTR
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
Figure 28: Tangent Line for tDS
DQS1
DQS#1
VDDQ
tDS
tDH
tDS
tDH
VIH(AC)min
VRrEeFgtioonAC
VIH(DC)min
Nominal
line
Tangent line
VREF(DC)
VIL(DC)max
VIL(AC)max
Tangent line
Nominal line
ÎTF
VREF to AC
region
ÎTR
VSS
Setup slew rate
falling signal
=
Tangent line (VREF[DC] - VIL[AC]max)
ÎTF
Setup slew rate
rising signal
=
Tangent line (VIH[AC]min - VREF[DC])
ÎTR
Note: 1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
PDF: 09005aef821ae8bf
1GbDDR2.pdf â Rev. T 02/10 EN
64
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2004 Micron Technology, Inc. All rights reserved.
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