MT9HVF12872KY Datasheet, PDF (9/17 Pages) Micron Technology – DDR2 SDRAM VLP Mini-RDIMM

512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
IDD Specifications
IDD Specifications
Table 9:
IDD Specifications and Conditions – 512MB
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
Parameter/Condition
Symbol
Operating one bank active-precharge current: ^tCK = ^tCK (IDD),
t_{RC =} t_{RC (IDD),} t_{RAS =} t_{RAS MIN (IDD); CKE is HIGH, S# is HIGH between}
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD0
Operating one bank active-read-precharge current: IOUT = 0mA;
BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD), ^tRC = ^tRC (IDD),
t_{RAS =} t_{RAS MIN (IDD),} t_{RCD =} t_{RCD (IDD); CKE is HIGH, S# is HIGH}
between valid commands; Address bus inputs are switching; Data
pattern is same as IDD4W
IDD1
Precharge power-down current: All device banks
idle; ^tCK = ^tCK (IDD); CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating
IDD2P
Precharge quiet standby current: All device banks idle;
t_{CK =} t_{CK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus}
inputs are stable; Data bus inputs are floating
Precharge standby current: All device banks idle; ^tCK = ^tCK (IDD); CKE
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD2Q
IDD2N
Active power-down current: All device banks open; Fast PDN exit
t_{CK =} t_{CK (IDD); CKE is LOW; Other control and address MR[12] = 0}
bus inputs are stable; Data bus inputs are floating
Slow PDN exit
MR[12] = 1
Active standby current: All device banks open; ^tCK = ^tCK (IDD),
t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between}
valid commands; Other control and address bus inputs are switching;
Data bus inputs are switching
IDD3P
IDD3N
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD),
t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between}
valid commands; Address bus inputs are switching; Data bus inputs are
switching
IDD4W
Operating burst read current: All device banks open; Continuous
burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; ^tCK = ^tCK (IDD),
t_{RAS =} t_{RAS MAX (IDD),} t_{RP =} t_{RP (IDD); CKE is HIGH, S# is HIGH between}
valid commands; Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: ^tCK = ^tCK (IDD); REFRESH command at every
t_{RFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands;}
Other control and address bus inputs are switching; Data bus inputs are
switching
IDD4R
IDD5
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and IDD6
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current: All device banks
interleaving reads; IOUT= 0mA; BL = 4, CL = CL (IDD), AL = ^tRCD (IDD) -
1 × ^tCK (IDD); ^tCK = ^tCK (IDD), ^tRC = ^tRC (IDD), ^tRRD = ^tRRD (IDD), ^tRCD =
t_{RCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address}
bus inputs are stable during deselects; Data bus inputs are switching
IDD7
-80E
-800
900
1,035
63
450
495
360
108
630
1,755
1,845
2,070
63
2,700
-667 -53E
810 720
945 855
63
63
405 360
450 405
315 270
108 108
585 495
1,530 1,260
1,620 1,305
1,620 1,530
63
63
2,160 2,025
-40E Units
720 mA
810 mA
63 mA
315 mA
360 mA
225 mA
108 mA
405 mA
1,035 mA
1,035 mA
1,485 mA
63 mA
1,980 mA
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
9
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