MT9HVF12872KY Datasheet, PDF (13/17 Pages) Micron Technology – DDR2 SDRAM VLP Mini-RDIMM

512MB, 1GB: (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Register and PLL Specifications
Table 14: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: IOUT = 3mA
Input leakage current: VIN = GND to VDDSPD
Output leakage current: VOUT = GND to VDDSPD
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
Symbol
VDDSPD
VIH
VIL
VOL
ILI
ILO
ISB
ICC_R
ICC_W
Min
1.7
VDDSPD × 0.7
–0.6
–
0.10
0.05
1.6
0.4
2
Max
3.6
VDDSPD + 0.5
VDDSPD × 0.3
0.4
3
3
4
1
3
Units
V
V
V
V
µA
µA
µA
mA
mA
Table 15: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +1.7V to +3.6V
Parameter/Condition
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
t_AA
t_BUF
t_DH
t_F
t_HD:DAT
t_HD:STA
t_HIGH
t_I
t_LOW
t_R
f_SCL
t_SU:DAT
t_SU:STA
t_SU:STO
t_WRC
Min
0.2
1.3
200
–
0
0.6
0.6
–
1.3
–
–
100
0.6
0.6
–
Max
0.9
–
–
300
–
–
–
50
–
0.3
400
–
–
–
10
Units
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
kHz
ns
µs
µs
ms
Notes
1
2
2
3
4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (^tWRC) is the time from a valid stop condition of a write
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
PDF: 09005aef81c9620b/Source: 09005aef81c961ec
HVF9C64_128x72K.fm - Rev. C 3/07 EN
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