MT28F1284W18 Datasheet, PDF (9/66 Pages) Micron Technology – 1.8V Low Voltage, Extended Temperature

8 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
Table 3: Ball Descriptions
58-BALL FBGA
NUMBERS
E8, D8, C8, B8, A8,
B7, A7, C7, A2, B2,
C2, A1, B1, C1, D2,
D1, D4, B6, A6, C6,
B3, C3, D7
B4
SYMBOL
A0–A22
CLK
C4
ADV#
E7
CE#
F8
OE#
C5
WE#
B5
RST#
D6
WP#
F7, E6, E5, G5, E4, G3,
E3, G1, G7, F6, F5, F4,
D5, F3, F2, E2
DQ0–
DQ15
D3
WAIT#
A4, G4
E1, G6
G2, G8
A3, F1
A5
VCC
VCCQ
VSSQ
VSS
VPP
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Output
Supply
Supply
Supply
Supply
Supply/
Input
DESCRIPTION
Address inputs: Inputs for the addresses during READ and WRITE
operations. All addresses are internally latched during WRITE cycles and
synchronous READ cycles. During asynchronous READ cycles, A0–A3 are not
internally latched.
Clock: Synchronizes the Flash device to the system operating frequency
during burst mode READ operations. When configured for burst mode
READs, address is latched on the first rising (or falling, depending upon the
read configuration register setting) CLK edge when ADV# is active or upon
a rising ADV# edge, whichever occurs first. CLK is ignored during
asynchronous page access READ and WRITE operations.¹
Address Valid: Indicates that a valid address is present on the address inputs.
Addresses are latched on the rising edge of ADV# during READ operations.¹
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device
goes into standby power mode if neither PROGRAM nor ERASE operations
are pending.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH,
the output buffers are disabled.
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW,
the cycle is either a WRITE to the command state machine (CSM) or to the
memory array.
Reset: When RST# is a logic LOW, the device is in reset mode, which drives
the outputs to High-Z and resets the write state machine. When RST# is at
logic HIGH, the device is in standard operation. When RST# transitions from
logic LOW to logic HIGH, the device resets all blocks to locked and defaults
to the read array mode.
Write Protect: Controls the lock down function of the flexible locking
feature.
Data Inputs/Outputs: Inputs array data on the second CE# and WE# cycle
during PROGRAM operation. Inputs commands to the command user
interface when CE# and WE# are active. DQ0–DQ15 output data when CE#
and OE# are active.
Wait: Provides data valid feedback during burst read access. The signal is
gated by CE#. The WAIT# signal polarity is set by RCR10 in the RCR.
Device Power Supply: [1.70V–1.95V] Supplies power for device operation.
I/O Power Supply: [1.70V–2.24] Supplies power for input/output buffers.
I/O Ground: Do not float any ground ball.
Supply Ground: Do not float any ground ball.
Program/Erase Enable: [0.9V–1.95V or 11.4V–12.6V] Operates as input at
logic levels to control complete device protection. Provides factory
programming compatibility, and acts as a current source, when driven to
11.4V–12.6V.
NOTE:
1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous/page mode.
09005aef80b425b4
MT28F1284W18_D.fm - Rev. D, 11/03 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.