MT18VDDT12872AG Datasheet, PDF (9/29 Pages) Micron Technology – DDR SDRAM UNBUFFERED DIMM

256MB, 512MB, 1GB (x72, ECC, DR), PC3200
184-PIN DDR SDRAM UDIMM
Table 6: Burst Definition Table
BURST
LENGTH
STARTING
COLUMN
ADDRESS
ORDER OF ACCESSES WITHIN
A BURST
TYPE =
TYPE =
SEQUENTIAL INTERLEAVED
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
00
0-1-2-3
0-1-2-3
4
01
1-2-3-0
1-0-3-2
10
2-3-0-1
2-3-0-1
11
3-0-1-2
3-2-1-0
A2 A1 A0
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
8
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-Ai select the two-data-ele-
ment block; A0 selects the first access within the block.
2. For a burst length of four, A2-Ai select the four-data-
element block; A0-A1 select the first access within the
block.
3. For a burst length of eight, A3-Ai select the eight-data-
element block; A0-A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
5. i = 9 (256MB, 512MB);
i = 9, 11 (1GB)
Table 7:
SPEED
-40B
CAS Latency (CL) Table
ALLOWABLE OPERATING
FREQUENCY (MHZ)
CL = 2
CL = 2.5
CL = 3
75 ≤ f ≤ 133 75 ≤ f ≤ 167 125 ≤ f ≤ 200
Figure 5: CAS Latency Diagram
T0
T1
CK#
CK
COMMAND
READ
NOP
T2 T2n T3 T3n
NOP
NOP
CL = 3
DQS
DQ
CK#
CK
COMMAND
T0
READ
DQS
DQ
CK#
CK
COMMAND
T0
READ
DQS
DQ
T1
NOP
CL = 2
T2 T2n T3 T3n
NOP
NOP
T1
T2 T2n T3 T3n
NOP
NOP
NOP
CL = 2.5
Burst Length = 4 in the cases shown
Shown with nominal ^{tAC, tDQSCK,} and ^tDQSQ
TRANSITIONING DATA
DON’T CARE
Operating Mode
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11 (for
256MB), or A7–A12 (512MB, 1GB) each set to zero, and
bits A0–A6 set to the desired values. A DLL reset is ini-
tiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (256MB), or A7 and A9–A12
(512MB, 1GB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values. Although not
required by the Micron device, JEDEC specifications
recommend when a LOAD MODE REGISTER com-
mand is issued to reset the DLL, it should always be
followed by a LOAD MODE REGISTER command to
select normal operating mode.
All other combinations of values for A7–A11
(256MB), or A7–A12 (512MB, 1GB) are reserved for
future use and/or test modes. Test modes and
pdf: 09005aef80814e61, source: 09005aef80a43eed
DDA18C32_64_128x72AG.fm - Rev. E 9/04 EN
9
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©2004 Micron Technology, Inc.