MT47H64M16HR-25H Datasheet, PDF (80/132 Pages) Micron Technology – DDR2 SDRAM MT47H256M4 – 32 Meg x 4 x 8 banks MT47H128M8 – 16 Meg x 8 x 8 banks MT47H64M16 – 8 Meg x 16 x 8 banks

1Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, on-
die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#
enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-
tions are controlled via the bits shown in Figure 36. The EMR is programmed via the LM
command and will retain the stored information until it is programmed again or the de-
vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-
ray, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time ^tMRD before initiating any subsequent opera-
tion. Violating either of these requirements could result in an unspecified operation.
Figure 36: EMR Definition
BA21 BA1 BA0 An2 A12
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
16 15 14 n 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MRS 0 Out RDQS DQS# OCD Program R_TT Posted CAS# R_TT ODS DLL
Extended mode
register (Ex)
E12 Outputs
0 Enabled
1 Disabled
E11 RDQS Enable
0
No
1
Yes
E6 E2 R_TT (Nominal)
0 0 R disabled
TT
01
75Ÿ
1 0 150Ÿ
11
50Ÿ
E0
DLL Enable
0 Enable (normal)
1 Disable (test/debug)
E1 Output Drive Strength
0
Full
1
Reduced
E10 DQS# Enable
0 Enable
1 Disable
E9 E8 E7 OCD Operation ⁴
0 0 0 OCD exit
0 0 1 Reserved
0 1 0 Reserved
1 0 0 Reserved
1 1 1 Enable OCD defaults
E5 E4 E3 Posted CAS# Additive Latency (AL) ³
000
0
001
1
010
2
011
3
100
4
101
5
110
6
111
Reserved
E15 E14
Mode Register Set
00
Mode register (MR)
0 1 Extended mode register (EMR)
1 0 Extended mode register (EMR2)
1 1 Extended mode register (EMR3)
Notes:
1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-
grammed to “0.”
2. Mode bits (En) with corresponding address balls (An) greater than E12 (A12) are re-
served for future use and must be programmed to “0.”
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization (page 86) section notes, during initialization of the
OCD operation, all three bits must be set to “1” for the OCD default state, then set to
“0” before initialization is finished.
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. X 10/11 EN
80
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