MT28F004B5 Datasheet, PDF (8/32 Pages) Micron Technology – FLASH MEMORY

4Mb
SMART 5 BOOT BLOCK FLASH MEMORY
COMMAND EXECUTION LOGIC (CEL)
The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.
DEEP POWER-DOWN MODE
To allow for maximum power conservation, the
MT28F004B5 and MT28F400B5 feature a very low cur-
rent, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 20µA at 5V VCC. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.
MEMORY ARCHITECTURE
The MT28F004B5 and MT28F400B5 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather
than the entire array are erased, total device endurance
is enhanced, as is system flexibility. Only the ERASE
function is block-oriented. All READ and WRITE opera-
tions are done on a random-access basis.
The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP# or
that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining six blocks do not require that either of these
two conditions be met before WRITE or ERASE
operations.
BOOT BLOCK
The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage
(VHH) of 12V or when the WP# pin is VIH. During a
WRITE or ERASE of the boot block, the RP# pin must be
held at VHH or the WP# pin held HIGH until the ERASE
or WRITE is completed. The VPP pin must be at VPPH (5V
or 12V) when the boot block is written to or erased.
WORD ADDRESS BYTE ADDRESS
3FFFFh
7FFFFh
128KB Main Block
30000h
2FFFFh
60000h
5FFFFh
128KB Main Block
20000h
1FFFFh
40000h
3FFFFh
128KB Main Block
10000h
0FFFFh
04000h
03FFFh
03000h
02FFFh
02000h
01FFFh
00000h
20000h
1FFFFh
08000h
07FFFh
06000h
05FFFh
04000h
03FFFh
00000h
96KB Main Block
8KB Parameter Block
8KB Parameter Block
16KB Boot Block
WORD ADDRESS BYTE ADDRESS
3FFFFh
7FFFFh
3E000h
3DFFFh
3D000h
3CFFFh
3C000h
3BFFFh
7C000h
7BFFFh
7A000h
79FFFh
78000h
77FFFh
16KB Boot Block
8KB Parameter Block
8KB Parameter Block
96KB Main Block
30000h
2FFFFh
60000h
5FFFFh
128KB Main Block
20000h
1FFFFh
40000h
3FFFFh
128KB Main Block
10000h
0FFFFh
20000h
1FFFFh
128KB Main Block
00000h
00000h
Bottom Boot
Top Boot
MT28F004B5/400B5xx-xxB
Figure 1
MT28F004B5/400B5xx-xxT
Memory Address Maps
4Mb Smart 5 Boot Block Flash Memory
F44_B.p65 – Rev. 7/02
8
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©2002, Micron Technology, Inc.