MT46H32M16LFBF-6ITC Datasheet, PDF (69/96 Pages) Micron Technology – 512Mb: x16, x32 Mobile Low-Power DDR SDRAM Features

512Mb: x16, x32 Mobile LPDDR SDRAM
READ Operation
Figure 30: Data Output Timing – ^tDQSQ, ^tQH, and Data Valid Window (x32)
CK# ^T1
CK
t_HP1
DQS0/DQS1/DQS2/DQS3
DQ (Last data valid)⁴
DQ⁴
DQ⁴
DQ⁴
DQ⁴
DQ⁴
DQ⁴
DQ (First data no longer valid)⁴
DQ (Last data valid)
DQ (First data no longer valid)
DQ and DQS, collectively^6,7
T2
T2n
T3
T3n
T4
t_HP1
t_HP1
t_HP1
t_DQSQ2,3
t_DQSQ2,3
t_HP1
t_DQSQ2,3
t_HP1
t_DQSQ2,3
t_QH5
T2
T2
T2
t_QH5
T2n
T2n
t_QH5
T3
T3
T2n
T3
t_QH5
T3n
T3n
T3n
Data valid Data valid
window window
Data valid
window
Data valid
window
Notes:
1. ^tHP is the lesser of ^tCL or ^tCH clock transition collectively when a bank is active.
2. DQ transitioning after DQS transitions define the ^tDQSQ window.
3. ^tDQSQ is derived at each DQS clock edge and is not cumulative over time; it begins with
DQS transition and ends with the last valid DQ transition.
4. Byte 0 is DQ[7:0], byte 1 is DQ[15:8], byte 2 is DQ[23:16], byte 3 is DQ[31:24].
5. ^tQH is derived from ^tHP: ^tQH = ^tHP - ^tQHS.
6. The data valid window is derived for each DQS transition and is ^tQH - ^tDQSQ.
7. DQ[7:0] and DQS0 for byte 0; DQ[15:8] and DQS1 for byte 1; DQ[23:16] and DQS2 for
byte 2; DQ[31:23] and DQS3 for byte 3.
PDF: 09005aef83dd2b3e
t67m_512mb_mobile_lpddr.pdf - Rev. H 06/13 EN
69
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