MT46V64M4_1 Datasheet, PDF (63/93 Pages) Micron Technology – Double Data Rate (DDR) SDRAM

256Mb: x4, x8, x16 DDR SDRAM
Operations
Data from any READ burst may be truncated with a BURST TERMINATE command, as
shown in Figure 31 on page 66. The BURST TERMINATE latency is equal to the CL, that
is, the BURST TERMINATE command should be issued x cycles after the READ
command where x equals the number of desired data element pairs (pairs are required
by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 32 on page 67. The ^tDQSS (NOM) case is shown; the
t_{DQSS (MAX) case has a longer bus idle time. (}t_{DQSS [MIN] and} t_{DQSS [MAX] are}
defined in the section on WRITEs.) A READ burst may be followed by, or truncated with,
a PRECHARGE command to the same bank provided that auto precharge was not acti-
vated.
The PRECHARGE command should be issued x cycles after the READ command, where
x equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 33 on page 68. Following the PRECHARGE
command, a subsequent command to the same bank cannot be issued until both ^tRAS
and ^tRP have been met. Part of the row precharge time is hidden during the access of the
last data elements.
PDF: 09005aef80768abb/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 256Mb DDR: Rev. O, Core DDR: Rev. B 1/09 EN
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