MT48LC4M32B2P-6G Datasheet, PDF (62/79 Pages) Micron Technology – SDR SDRAM

128Mb: x32 SDRAM
PRECHARGE Operation
Figure 35: READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
Command
READ - AP
Bank n
NOP
NOP
Internal ^{Bank n}
Page
active
READ with burst of 4
States
Bank m
Page active
NOP
WRITE - AP
Bank m
NOP
NOP
Interrupt burst, precharge
tRP _{- bank n}
WRITE with burst of 4
NOP
Idle
tWR _{- bankm}
Write-back
Address
Bank n,
Col a
Bank m,
Col d
DQM¹
DQ
D_OUT
D_IN
D_IN
D_IN
D_IN
CL = 3 (bank n)
Transitioning data
Don’t Care
Note: 1. DQM is HIGH at T2 to prevent D_OUTa + 1 from contending with D_INd at T4.
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
62
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