MT48LC4M32B2P-6G Datasheet, PDF (44/79 Pages) Micron Technology – SDR SDRAM

128Mb: x32 SDRAM
READ Operation
Figure 16: Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
T6
CLK
Command READ
NOP
Address
Bank,
Col n
DQ
CL = 2
T0
T1
CLK
NOP
NOP
READ
NOP
X = 1 cycle
Bank,
Col b
NOP
D_OnUT
Dn _O+U1T
D_OUT
n+2
Dn _O+U3T
D_OUT
b
T2
T3
T4
T5
T6
T7
Command READ
NOP
NOP
NOP
READ
NOP
NOP
NOP
Address
Bank,
Col n
X = 2 cycles
Bank,
Col b
DQ
D_OUT
D_OUT
D_OUT
D_OUT
D_OUT
CL = 3
Transitioning data
Note: 1. Each READ command can be issued to any bank. DQM is LOW.
Don’t Care
PDF: 09005aef80872800
128mb_x32_sdram.pdf - Rev. U 04/13 EN
44
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