MT9E001 Datasheet, PDF (61/97 Pages) Micron Technology – 1/2.5-Inch CMOS Digital Image Sensor

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Preliminary
MT9E001: 1/2.5-Inch 8-Mp Digital Image Sensor
Register Description
Table 19: 1: SMIA Parameter Limits (continued)
Reg. #
R4356
R0x1104
R4358
R0x1106
R4360
R0x1108
R4362
R0x110A
R4364
R0x110C
R4366
R0x110E
R4368
R0x1110
R4370
R0x1112
R4372
R0x1114
R4374
R0x1116
R4376
R0x1118
R4378
R0x111A
R4380
R0x111C
R4382
R0x111E
R4384
R0x1120
R4386
R0x1122
R4388
R0x1124
R4390
R0x1126
R4392
R0x1128
R4394
R0x112A
R4396
R0x112C
Bits
Default
Name
Frame Sync'd Bad Frame
15:0
0x4240
max_ext_clk_freq_mhz_1 (RO)
N
N
FLP32. Maximum external clock frequency into PLL is 48 MHz. Read-only.
15:0
0x0000
max_ext_clk_freq_mhz_2 (RO)
N
N
FLP32. Maximum external clock frequency into PLL is 48 MHz. Read-only.
15:0
0x0001
min_pre_pll_clk_div (RO)
N
N
Minimum clock divisor applied to PLL input clock. Read-only.
15:0
0x0040
max_pre_pll_clk_div (RO)
N
N
Maximum clock divisor applied to PLL input clock. Read-only.
15:0
0x4000
min_pll_ip_freq_mhz_1 (RO)
N
N
FLP32. Minimum clock frequency into the PFD of the PLL is 2 MHz. Read-only.
15:0
0x0000
min_pll_ip_freq_mhz_2 (RO)
N
N
FLP32. Minimum clock frequency into the PFD of the PLL is 2 MHz. Read-only.
15:0
0x41C0
max_pll_ip_freq_mhz_1 (RO)
N
N
FLP32. Maximum clock frequency into the PFD of the PLL is 22.5 MHz. Read-only.
15:0
0x0000
max_pll_ip_freq_mhz_2 (RO)
N
N
FLP32. Maximum clock frequency into the PFD of the PLL is 22.5 MHz. Read-only.
15:0
0x0020
min_pll_multiplier (RO)
N
N
Minimum multiplier applied by PLL. Read-only.
15:0
0x0100
max_pll_multiplier (RO)
N
N
Maximum multiplier applied by PLL. Read-only.
15:0
0x43C0
min_pll_op_freq_mhz_1 (RO)
N
N
FLP32. Minimum output frequency supported by the PLL is 160 MHz. Read-only.
15:0
0x0000
min_pll_op_freq_mhz_2 (RO)
N
N
FLP32. Minimum output frequency supported by the PLL is 160 MHz. Read-only.
15:0
0x4440
max_pll_op_freq_mhz_1 (RO)
N
N
FLP32. Maximum output frequency supported by the PLL is 768 MHz. Read-only.
15:0
0x0000
max_pll_op_freq_mhz_2 (RO)
N
N
FLP32. Maximum output frequency supported by the PLL is 768 MHz. Read-only.
15:0
0x0001
min_vt_sys_clk_div (RO)
N
N
The video timing sys_clk has a fixed divisor. Read-only.
15:0
0x0001
max_vt_sys_clk_div (RO)
N
N
The video timing sys_clk has a fixed divisor. Read-only.
15:0
0x43C0
min_vt_sys_clk_freq_mhz_1 (RO)
N
N
FLP32. Minimum frequency for the video timing sys_clk is 40 MHz.
15:0
0x0000
min_vt_sys_clk_freq_mhz_2 (RO)
N
N
FLP32. Minimum frequency for the video timing sys_clk is 40 MHz.
15:0
0x4440
max_vt_sys_clk_freq_mhz_1 (RO)
N
N
Maximum frequency for the video timing sys_clk is 192 MHz. Read-only.
15:0
0x0000
max_vt_sys_clk_freq_mhz_2 (RO)
N
N
Maximum frequency for the video timing sys_clk is 192 MHz. Read-only.
15:0
0x42C0
min_vt_pix_clk_freq_mhz_1 (RO)
N
N
FLP32. Minimum frequency for video timing pix_clk is 10 MHz. Read-only.
PDF: 09005aef8210fa55/Source: 09005aef8210f91a
MT9E001__4reg_desc.fm - Rev. C 10/06 EN
61
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