MT46V32M4 Datasheet, PDF (6/8 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

GENERAL DESCRIPTION
The DDR333 SDRAM is a high-speed CMOS, dy-
namic random-access memory that operates at a fre-
quency of 167 MHz (^tCK=6ns) with a peak data trans-
fer rate of 333Mb/s/p. DDR333 continues to use the
JEDEC standard SSTL_2 interface and the 2n-prefetch
architecture.
The standard DDR200/DDR266 data sheets also
pertain to the DDR333 device and should be referenced
for a complete description of DDR SDRAM function-
PRELIMINARY
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
ality and operating modes. However, to meet the faster
DDR333 operating frequencies, some of the AC timing
parameters are slightly tighter. This addendum data
sheet will concentrate on the key differences required
to support the enhanced speeds.
In addition to the standard 66-pin TSOP package,
a 60-ball FBGA package is utilized for DDR333. This
JEDEC-defined package promotes better package para-
sitic parameters and a smaller footprint.
CAPACITANCE (FBGA)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T_A ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL MIN MAX UNITS NOTES
DCIO
DCIO
DCIO
DCI1
DCI2
CIO
CI1
CI2
CI3
–
–
–
–
–
3.50
1.50
1.50
1.50
0.50
0.50
0.50
0.50
0.25
4.00
2.50
2.50
2.50
pF 13, 24
pF 13, 24
pF 13, 29
pF 13, 29
p F 13, 29
pF
13
pF
13
pF
13
pF
13
CAPACITANCE (TSOP)
(Notes: 1-5, 14-17, 33; notes appear in DDR200/266 data sheets)
(0°C ≤ T_A ≤ 70°C; VDDQ = +2.5V ±0.2V, VDD = +2.5V ±0.2V)
PARAMETER
Delta Input/Output Capacitance:
DQs, DQS, DM (for x4 or x8 devices)
DQ0-DQ7, LDQS, LDM (for lower byte of x16 devices),
DQ8-DQ15, UDQS, UDM (for upper byte of x16 devices)
Delta Input Capacitance: Command and Address
Delta Input Capacitance: CK, CK#
Input/Output Capacitance: DQs, DQS, DM (LDQS, LDM, UDM)
Input Capacitance: Command and Address
Input Capacitance: CK, CK#
Input Capacitance: CKE
SYMBOL MIN MAX UNITS NOTES
DCIO
DCIO
DCIO
DCI1
DCI2
CIO
CI1
CI2
CI3
– 0.50 pF 13, 24
– 0.50 pF 13, 24
– 0.50 pF 13, 24
– 0.50 pF 13, 29
– 0.25 p F 13, 29
4.0 5.0
pF
13
2.0 3.0
pF
13
2.0 3.0 p F 13
2.0 3.0
pF
13
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.