MT46V32M4 Datasheet, PDF (1/8 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• 167 MHz Clock, 333 Mb/s/p data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• ^tRAS lockout (^tRAP = ^tRCD)
• Backwards compatible with DDR200 and DDR266
OPTIONS
PART NUMBER
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks) 32M4
16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8
8 Meg x 16 (2 Meg x 16 x 4 banks) 8M16
• Plastic Package
66-Pin TSOP (OCPL)
TG
60-Ball FBGA (16x9mm)
FJ
• Timing - Cycle Time
6ns @ CL = 2.5 (DDR333B–FBGA)¹
6ns @ CL = 2.5 (DDR333B–TSOP)¹
7.5ns @ CL = 2 (DDR266A)²
-6
-6T
-75Z
• Self Refresh
Standard
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
PRELIMINARY^‡
128Mb: x4, x8, x16
DDR333 SDRAM Addendum
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and ^tRAS lockout
for improved timing performance. The 128Mb, DDR333
device will support an (^tREFI) average periodic refresh
interval of 15.6µs.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 128Mb data sheet provides full specifi-
cations and functionality unless specified herein.
CONFIGURATION
Architecture 32 Meg x 4
16 Meg x 8
8 Meg x 16
Configuration
8 Meg x 4 x 4 banks 4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
Refresh Count
4K
4K
4K
Row Addressing
4K (A0–A11)
4K (A0–A11)
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
ColumnAddressing 2K (A0–A9, A11)
1K (A0–A9)
512 (A0– A8)
KEY TIMING PARAMETERS³
SPEED
CLOCK RATE DATA-OUT ACCESS DQS-DQ
GRADE CL = 2¹ CL = 2.5¹ WINDOW² WINDOW SKEW
-6 133 MHz 167 MHz 2.15ns ±0.70ns +0.35ns
-6T 133 MHz 167 MHz 2.0ns ±0.75ns +0.45ns
-75Z 133 MHz 133 MHz 2.5ns ±0.75ns +0.50ns
NOTE:
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. Slower speeds are included in the 128Mb base data
sheet (-75, -8).
256Mb: x4, x8, x16 DDR333 SDRAM
128Mx4x8x16DDR333.p65 – Rev. A; Pub. 10/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION AND DATA SHEET SPECIFICATIONS.