MT46V32M4-1 Datasheet, PDF (59/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
INITIALIZE AND LOAD MODE REGISTERS
VDD
VDDQ
VTT¹
VREF
t_VTD1
CK#
CK
CKE
COMMAND⁶⁶
DM
A0-A9,
A11
A10
BA0, BA1
((
))
((
))
((
))
((
))
T0
T1
((
))
((
t_CH t_CL
))
LVCMOS
LOW LEVEL _{( (}
))
t_IS ^tIH
tIS tIH
NOP
t_CK
((
))
((
))
((
))
PRE
((
))
((
))
((
))
((
))
((
))
ALL BANKS ( (
))
((
))
tIS tIH
((
))
((
))
T2
((
))
((
))
((
))
((
))
((
))
LMR
((
))
((
))
((
))
tIS tIH
((
))
CODE
((
))
tIS tIH
((
))
CODE
((
))
tIS tIH
((
BA0 = H, ^{) )}
BA1 = L ( (
))
Ta0
((
))
((
))
Tb0
((
))
((
))
((
))
((
))
((
))
LMR
((
))
((
))
((
))
((
))
((
))
((
))
PRE
((
))
((
))
((
))
((
((
))
))
CODE
((
((
))
))
CODE
( ( ^{ALL BANKS} ( (
))
))
((
((
))
))
t_IS t_IH
((
((
BA0 = L, ^{) )}
))
BA1 = L ( (
((
))
))
Tc0
((
))
((
))
((
))
((
))
((
))
AR
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
Td0
Te0
((
))
((
))
((
))
((
))
((
AR
))
((
ACT5
))
((
))
((
))
((
))
((
RA
))
((
))
((
RA
))
((
))
((
BA
))
DQS
((
High-Z
))
((
((
((
((
((
((
))
))
))
))
))
))
DQ
((
High-Z
))
((
((
((
((
((
((
))
))
))
))
))
))
T = 200µs
Power-up: VDD and CK stable
tRP
tMRD
tMRD
Load Extended
Mode Register
Load Mode
Register²
tRP
200 cycles of CK³
tRFC
tRFC5
DON’T CARE
NOTE:
1. VTT is not applied directly to the device; however, ^tVTD should be greater than or equal to zero to avoid device latch-up.
VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if
VDD/VDDQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin.
2. Reset the DLL with A8 = H.
3. ^tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.
4. The two AUTO REFRESH commands at Tc0 and Td0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.
5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank.
6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row
Address, BA = Bank Address
TIMING PARAMETERS
SYMBOL
t_CH
t_CL
t_{CK (2.5)}
t_{CK (2)}
t_IH
-75Z
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
7.5
13
1
-75
MIN MAX
0.45 0.55
0.45 0.55
7.5
13
10
13
1
-8
MIN MAX
0.45 0.55
0.45 0.55
8
13
10
13
1.1
UNITS
t_CK
t_CK
ns
ns
ns
SYMBOL
t_IS
t_MRD
t_RFC
t_RP
t_VTD
-75Z
MIN MAX
1
15
75
20
0
-75
MIN MAX
1
15
75
20
0
-8
MIN MAX
1.1
16
80
20
0
UNITS
ns
ns
ns
ns
ns
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
59
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©2001, Micron Technology, Inc.