MT46V32M4-1 Datasheet, PDF (1/68 Pages) Micron Technology – DOUBLE DATA RATE DDR SDRAM

DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
MARKING
32M4
16M8
8M16
• Plastic Package – OCPL
66-pin TSOP
TG
(400 mil width, 0.65mm pin pitch)
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)¹
7.5ns @ CL = 2.5 (DDR266B)²
10ns @ CL = 2 (DDR200)³
-75Z
-75
-8
• Self Refresh
Standard
Low Power
none
L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
PRELIMINARY^‡
128Mb: x4, x8, x16
DDR SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4
x8
x16
VDD
VDD
VDD
1
NC DQ0 DQ0
2
VDDQ VDDQ VDDQ
3
NC
NC DQ1
4
DQ0 DQ1 DQ2
5
VSSQ VSSQ VssQ
6
NC
NC DQ3
7
NC DQ2 DQ4
8
VDDQ VDDQ VDDQ
9
NC
NC DQ5
10
DQ1 DQ3 DQ6
11
VSSQ VSSQ VssQ
12
NC
NC DQ7
13
NC
NC
NC
14
VDDQ VDDQ VDDQ
15
NC
NC LDQS
16
NC
NC NC
17
VDD
VDD
VDD
18
NC DNU DNU
19
NC
NC LDM
20
WE# WE# WE#
21
CAS# CAS# CAS#
22
RAS# RAS# RAS#
23
CS# CS# CS#
24
NC
NC
NC
25
BA0 BA0 BA0
26
BA1 BA1 BA1
27
A10/AP A10/AP A10/AP
28
A0
A0
A0
29
A1
A1
A1
30
A2
A2
A2
31
A3
A3
A3
32
VDD
VDD
VDD
33
x16
x8
x4
66
VSS
VSS
VSS
65
DQ15 DQ7 NC
64
VSSQ VSSQ VSSQ
63
DQ14 NC
NC
62
DQ13 DQ6 DQ3
61
VDDQ VDDQ VDDQ
60
DQ12 NC
NC
59
DQ11 DQ5 NC
58
VSSQ VSSQ VSSQ
57
DQ10 NC
NC
56
DQ9 DQ4 DQ2
55
VDDQ VDDQ VDDQ
54
DQ8 NC
NC
53
NC
NC
NC
52
VSSQ VSSQ VSSQ
51
UDQS DQS DQS
50
DNU DNU DNU
49
VREF
VREF
VREF
48
VSS
VSS
VSS
47
UDM DM DM
46
CK# CK# CK#
45
CK
CK
CK
44
CKE CKE CKE
43
NC
NC
NC
42
NC
NC
NC
41
A11 A11 A11
40
A9
A9
A9
39
A8
A8
A8
38
A7
A7
A7
37
A6
A6
A6
36
A5
A5
A5
35
A4
A4
A4
34
VSS
VSS
VSS
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
2K (A0–A9, A11)
16 Meg x 8
8 Meg x 16
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K
4K
4K (A0–A11)
4K (A0–A11)
4 (BA0, BA1)
4 (BA0, BA1)
1K (A0–A9)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
DATA-OUT ACCESS DQS-DQ
GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW
-75Z 133 MHz
-75 100 MHz
-8 100 MHz
133 MHz
133 MHz
125 MHz
2.5ns
2.5ns
3.4ns
±0.75ns
±0.75ns
±0.8ns
+0.5ns
+0.5ns
+0.6ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.