MT48H32M16LF Datasheet, PDF (53/73 Pages) Micron Technology – 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM

512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM
Timing Diagrams
Timing Diagrams
Figure 36: Initialize and Load Mode Register
((
CLK
))
((
))
((
CKE
))
((
))
((
COMMAND¹
))
((
))
((
))
DQM
((
))
((
A0-A9, A11
))
((
))
T0
t_CK
t_CKS t_CKH
t_CMS t_CMH
NOP
T1
Tn + 1
To + 1
Tp + 1
Tq + 1
Tr + 1
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
PRE
((
AR
((
AR
((
LMR
((
LMR
((
VALID _{( (}
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
((
((
((
))
))
))
))
))
))
tA_S tAH
((
((
((
((
((
((
))
))
))
))
))
))
((
((
((
CODE
((
CODE
((
VALID
((
))
))
))
))
))
))
((
A10
))
((
))
((
))
BA0, BA1
((
))
ALL BANKS _{( (}
((
((
((
((
((
))
((
))
((
))
))
))
))
((
CODE
((
CODE
((
VALID
((
))
))
))
))
))
))
t_AS tAH
t_AS t_AH
((
((
((
((
((
((
))
((
))
((
) ) _{BA0 = L,} ) ) _BBAA00==LL,, ) )
((
BA1 = L ( (
BBAA11==HL ( (
))
VALID
((
))
))
))
))
))
))
((
DQ
))
High-Z
T = 100µs
Power-up:
VDD and
CLK stable
((
))
t_RP
Precharge
all banks
((
))
t_RFC2
((
((
((
((
))
))
))
))
t_RFC2
t_MRD3
t_MRD3
Load Mode Load Extended
Register Mode Register
DON’T CARE
Notes:
1. PRE = PRECHARGE command, AR = AUTO REFRESH command, LMR = LOAD MODE REGISTER
command.
2. Only NOPs or COMMAND INHIBITs may be issued during ^tRFC time.
3. At least one NOP or COMMAND INHIBIT is required during ^tMRD time.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
53
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