JS28F256P33BFE Datasheet, PDF (53/90 Pages) Micron Technology – NumonyxTM StrataFlash Embedded Memory

P33-65nm
.
Figure 20: Synchronous Single-Word Array or Non-array Read Timing
CLK [C]
R301
R306
R2
Address [A]
ADV# [V]
R105
R101
R104
R106
R303
R102
R3
R8
CE# [E]
R7
R9
OE# [G]
R15
WAIT [T]
R307
R312 R17
Data [D/Q]
R4
R304
R305
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Figure 21: Continuous Burst Read, showing an Output Delay Timing
CLK [C]
R301
R302
R306
R304
R304
R304
R2
R101
Address [A]
ADV# [V]
R105
R106
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R312
WAIT [T]
Data [D/Q]
R304
R4
R7
R305
R305
R305
R305
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
2.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned. See Section 11.1.3, “End of Word Line (EOWL) Considerations” on
page 37 for more information
Datasheet
53
Aug 2009
Order Number:320003-08